Slew-Enhanced Op-Amp Input Stage With Linear Current Mirrors
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Solution Overview
Problem
Slew-enhanced operational amplifiers face issues with open-loop gain diminishment under output loading and nonlinearity between npn and pnp current mirrors, limiting gain and causing signal compliance problems near the low voltage rail.
Innovation Solution
The implementation of complimentary differential input transconductors, npn-pnp, and pnp-npn current mirrors, along with common-mode control currents, to enhance output currents and maintain zero quiescent current, thereby improving signal linearity and compliance with the low voltage rail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a classic rail-to-rail output stage is used with a slew-enhanced input stage, then the amplifier can drive output current, but the open-loop gain diminishes badly with output loading and is limited to around 30 with 150% load
Solution Approach 1:
The patent divides the current amplification function into multiple independent current mirror stages (first npn-pnp current mirror, second npn-pnp current mirror, first pnp-npn current mirror, second pnp-npn current mirror) rather than using a single classic output stage. This segmentation allows each mirror to contribute to gain while maintaining output drive capability, resolving the contradiction between power and measurement precision.
Solution Approach 2:
The patent introduces intermediate current mirrors as mediators between the input stage and output stage. These current mirrors (particularly the npn-pnp and pnp-npn combinations) act as buffer stages that maintain high gain while providing the necessary current amplification for output loading, preventing direct loading effects from degrading the open-loop gain.
2Productivity
If npn and pnp current mirrors are used in the input stage, then the amplifier can operate in class-AB mode with independent slew currents, but nonlinearity occurs between the current mirrors limiting gain and causing signal compliance problems near the low voltage rail
Solution Approach 1:
The patent applies different transistor types (npn and pnp) in specific local configurations within the current mirrors to optimize performance in different regions of operation. The npn-pnp and pnp-npn current mirror combinations are strategically arranged to maintain linearity in the critical low-voltage region while preserving class-AB slew rate capability, addressing the nonlinearity problem without sacrificing productivity.
Solution Approach 2:
The patent uses asymmetric combinations of npn and pnp transistors in the current mirrors rather than symmetric single-type configurations. This asymmetry allows the circuit to compensate for the inherent nonlinearity of individual transistor types by balancing their characteristics across the differential pair, improving signal linearity while maintaining high slew rate capability.
Data Source
AI summary
Provided herein are input stages, and operation amplifiers including input stages. In an embodiment, an input stage includes a complimentary differential input transconductor, first and second npn-pnp current mirrors, and first and second pnp-npn current mirrors. The complimentary differential input transconductor includes a pair of differential inputs that accept a pair of voltage signals, a first pair of complimentary differential outputs that output current signals I1 and I2, and a second pair of complimentary differential outputs that output current signals I3 and I4. Each current mirror accepts one of the current signals I1, I2, I3 and I4, and outputs a pair of current signals (e.g., I1′ and I1″) that are proportional to the accepted current signal (e.g., I1). Current signals I1′ and I3′ are added to produce a first output current (Iout) of the input stage. Current signals I2′ and I4′ are added to produce a second output current (Iout_bar) of the input stage.