Slice-Based Allocation History Buffer for CPU Register Management
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Solution Overview
Problem
Current history buffer systems in computer processing units require tracking of instruction tags (ITAG) for previous writes to registers, leading to increased complexity and unnecessary comparisons for flush and restore operations, particularly in out-of-order execution scenarios.
Innovation Solution
A slice-based allocation history buffer system that organizes entries by logical register (LREG) groupings, utilizing an age array to determine relative ages and reduce the need for ITAG tracking, enabling efficient flush and restore operations by aligning instructions and managing register mappings effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional history buffer systems track instruction tags (ITAG) for previous writes to registers, then flush and restore operations can be performed, but device complexity and unnecessary comparisons increase
Solution Approach 1:
The history buffer is divided into multiple slices, where each slice handles a specific subset of logical registers. This segmentation allows the system to track only the necessary register mappings for each slice rather than tracking all registers globally, reducing the complexity of ITAG tracking while maintaining reliable flush and restore operations for each slice's assigned registers
Solution Approach 2:
The patent extracts and removes the ITAG tracking mechanism from the history buffer system. Instead of storing and comparing instruction tags for each register write, the system uses a simplified approach where the history buffer stores only the necessary mapping information (physical register to logical register mappings) and uses the age array to determine the order of operations, eliminating unnecessary comparisons while preserving flush and restore functionality
2Reliability
If the history buffer stores complete mapping information for all registers, then accurate restore operations are enabled, but the quantity of stored information increases
Solution Approach 1:
The history buffer is segmented into multiple slices, each managing a specific portion of the register space. This allows the system to store mapping information only for the registers assigned to each slice rather than maintaining complete mapping information for all registers globally, reducing the total quantity of stored information while ensuring accurate restore operations for each slice's registers
Solution Approach 2:
Each history buffer slice maintains mapping information with the specific quality and granularity needed for its assigned register subset. The system stores only the necessary mapping details (physical register, logical register, age) for each slice's registers rather than complete mapping information for all registers, reducing storage requirements while maintaining sufficient accuracy for restore operations
Data Source
AI summary
A multi-slice processor comprising a high-level structure and history buffer. Write backs are no longer associated with the history buffer and the history buffer comprises slices determined by logical register allocation. The history buffer receives a register pointer entry and either releases or restores the entry with functional units comprised in the history buffer.