Slice-Aware Control Storage for Low-Latency Image Frame Output
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Solution Overview
Problem
Existing computing devices face challenges in reducing display latency when decoding and displaying image frames, as they often require waiting for the entire image to be reconstructed before outputting it, which can hinder user experience.
Innovation Solution
The implementation of an image data control storage unit that stores slice information, allowing for the logical partitioning of image frames into tiles and slices, enabling the use of slice identifiers to retrieve and reconstruct tile rows more efficiently, thereby reducing reconstruction latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the entire image frame is decoded and reconstructed before outputting, then the decoding process is simple and complete, but display latency increases and user experience deteriorates
Solution Approach 1:
The patent divides the image frame into multiple tiles, and each tile into multiple slice rows. This segmentation allows the decoder to process and output only the required portion of the image (e.g., current tile row) without waiting for the entire image to be decoded, thereby reducing display latency while maintaining manageable decoding complexity through structured division.
Solution Approach 2:
The patent stores slice information in advance in a control storage unit during the decoding process. This preliminary storage of slice identifiers and information allows the processor to quickly retrieve and use the necessary data when generating output, eliminating the need to wait for complete image reconstruction and reducing display latency.
2Productivity
If slice information is stored and processed efficiently, then display latency is reduced and user experience is improved, but the control storage unit and processing complexity increase
Solution Approach 1:
The patent organizes the control storage unit with control entries that are segmented by tile row, with each entry containing only the necessary slice information for that specific tile row. This segmented organization improves processing efficiency by allowing selective retrieval of relevant slice information without managing a complex monolithic storage structure.
Solution Approach 2:
The patent extracts only the essential slice information (slice identifiers and related metadata) from the complete decoded image data and stores it separately in the control storage unit. This extraction approach enables efficient retrieval and processing of specific slice information without handling the entire image data, thereby improving productivity while keeping the control storage unit relatively simple.
3Loss of time
If the image frame is divided into tiles and slices, then display latency is reduced by enabling progressive output, but the device complexity and control mechanisms increase
Solution Approach 1:
The patent implements a hierarchical segmentation structure where the image frame is divided into tiles, and each tile is divided into slice rows. This multi-level segmentation enables progressive output by allowing the decoder to process and output complete slice rows independently, reducing reconstruction latency while maintaining a structured and manageable complexity through clear hierarchical organization.
Solution Approach 2:
The patent introduces a control storage unit as an intermediary between the decoder and the output generation process. This intermediary stores slice information and provides it to the processor, which then uses it to generate output efficiently. The control storage unit acts as a mediator that simplifies the interaction between decoding and output operations, reducing overall system complexity while enabling low-latency progressive display.
Data Source
AI summary
A device includes a first memory configured to include a control storage unit associated with an image frame. The device also includes a processor configured to receive a bitstream representing multiple tiles of the image frame. Each of the multiple tiles includes a plurality of tile rows of coding units. The processor is also configured to, for a tile row of a tile of the multiple tiles, generate a control entry of the control storage unit. The control entry includes tile row information that indicates a slice identifier of a slice that includes at least a portion of the tile row.