Interface Slice Merging Circuit for Timing-Aligned Die Links
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Solution Overview
Problem
In semiconductor-based digital electronic devices, the integration of multiple dies in 2.5D semiconductor devices leads to delays in data transmission due to varying delays across interface circuit slices, which affects the overall performance and functionality.
Innovation Solution
An integrated circuit die with multiple interface circuit slices and a merging circuit that splits and aligns data streams to mitigate these delays by merging sub-data streams back into a synchronized transmission data stream, providing a consistent application layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple interface circuit slices are used to receive sub-data streams in parallel, then data transmission capacity is improved, but timing delays vary across different slices causing synchronization issues
Solution Approach 1:
The receiving interface is segmented into multiple interface circuit slices (first interface circuit slice, second interface circuit slice, etc.), each independently receiving a separate sub-data stream. This segmentation enables parallel data reception, increasing overall data transmission capacity while allowing individual slices to be optimized for their specific timing characteristics.
Solution Approach 2:
A merging circuit is introduced as an intermediary component that receives sub-data streams from multiple interface circuit slices, performs timing alignment to compensate for delay variations, and merges the aligned streams back into a unified data stream. This intermediary resolves the synchronization issue caused by varying delays across parallel slices.
2Productivity
If data streams are split into multiple sub-data streams for parallel processing, then transmission efficiency is improved, but the complexity of merging and synchronizing streams increases
Solution Approach 1:
The data transmission system is segmented into distinct functional components: a splitting circuit that divides the original data stream into multiple sub-data streams, multiple interface circuit slices that process these streams in parallel, and a merging circuit that recombines them. This segmentation distributes complexity across modular components rather than concentrating it in a single complex unit.
Solution Approach 2:
The merging circuit incorporates timing alignment functionality that monitors and adjusts the timing of sub-data streams from different interface slices. This feedback mechanism automatically compensates for delay variations, reducing the need for complex manual synchronization and simplifying the overall merging operation.
Data Source
AI summary
An electronic system, an integrated circuit die and an operation method thereof are provided. The integrated circuit die includes a plurality of interface circuit slices and a merging circuit. The transmission data stream sent from the transmitter die is split into a plurality of sub-data streams. Each of the interface circuit slices provides a physical layer to receive the corresponding one of the sub-data streams. The merging circuit is coupled to the interface circuit slices to receive the sub-data streams. The merging circuit merges the sub-data streams from the interface circuit slices back to the original data corresponding to the transmission data stream to be provided to an application layer. The merging circuit aligns the sub-data streams from the interface circuit slices in timing to mitigate different delays of the interface circuit slices.