Slice Packing Validity Checking in Programmable Devices
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Solution Overview
Problem
Existing methods for determining slice packing validity in programmable logic devices, such as FPGAs, are complex and require custom-coded solutions for each slice topology, making debugging difficult and inefficient.
Innovation Solution
A method that generates Boolean equations based on slice topology and circuit fragments to determine whether a valid solution exists for mapping circuit elements to slices, using a SAT-solver to indicate slice packing validity, thereby avoiding the need for custom-coded solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If custom-coded solutions are developed for each slice topology, then slice packing validity can be checked, but device complexity and debugging difficulty increase
Solution Approach 1:
The patent applies universality by creating a single generic validation framework that works across multiple slice topologies. Instead of developing custom-coded solutions for each slice architecture, the system uses a unified approach that can validate packing correctness for any slice type, thereby reducing device complexity while maintaining reliability
Solution Approach 2:
The patent introduces an intermediary validation mechanism that acts as a mediator between the slice packing process and the final validation result. This intermediary layer provides a standardized interface for checking packing validity without requiring custom code for each topology, thus reducing complexity while ensuring reliable validation
2Reliability
If complex validation tools are used to ensure slice packing correctness, then packing validity can be determined, but ease of operation and debugging become difficult
Solution Approach 1:
The patent implements self-service by enabling the validation system to automatically check and report slice packing validity without requiring complex manual debugging processes. The generic validation framework autonomously determines whether packing is correct, simplifying operation and improving ease of debugging while maintaining reliability
3Productivity
If heuristics are used to cluster circuit elements into slices, then productivity improves, but manufacturing precision of the mapping may be compromised
Solution Approach 1:
The patent applies preliminary action by performing validation checks after the heuristic packing process has clustered circuit elements into slices. This post-packing validation ensures that even though heuristics were used for rapid clustering, the final mapping accuracy is verified to meet precision requirements, thus maintaining both productivity and manufacturing precision
Data Source
AI summary
A method of determining validity of slice packing for a programmable device can include identifying a slice topology for a slice, identifying a circuit fragment assigned to the slice, and generating a set of Boolean equations describing conditions for mapping the circuit fragment to the slice according to the slice topology. The method further can include determining whether a solution to the set of Boolean equations exists and indicating whether the slice is validly packed according to whether a solution for the set of Boolean equations is determined.