Sliced Charge Pump Control in Fractional-N PLLs for Lower Phase Noise
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Solution Overview
Problem
Existing fractional-N phase locked loops (PLLs) face challenges in reducing phase noise without increasing power consumption or circuit area, and often require complex calibration or scrambling mechanisms to avoid noise folding issues.
Innovation Solution
The proposed solution involves a fractional-N PLL with a sliced charge pump control method, where the charge pump is sliced into multiple current sources to reduce timing mismatch and noise folding concerns, thereby eliminating the need for complex calibration mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a frequency divider varies the divisor in a random-like manner to synthesize non-integer frequencies, then fractional-N PLL functionality is achieved, but phase noise (in-band and out-band) is introduced
Solution Approach 1:
The frequency divider is segmented into multiple parallel dividers (first frequency divider and second frequency divider) with different division ratios. This segmentation allows the system to achieve fractional-N PLL functionality while reducing phase noise through deterministic switching between dividers rather than random-like variation.
2Object-generated harmful factors
If calibration mechanisms or scrambling mechanisms (such as PRPS) are introduced to reduce phase noise, then noise folding issues are avoided, but circuit area and power consumption greatly increase
Solution Approach 1:
The system segments the frequency divider into multiple parallel dividers with different division ratios, eliminating the need for complex calibration or scrambling mechanisms. This segmentation approach inherently reduces phase noise without requiring additional calibration circuits or PRPS mechanisms, thereby avoiding the associated area and power penalties.
Solution Approach 2:
Instead of using a single frequency divider with random-like divisor variation and then applying calibration/scrambling to fix the resulting phase noise, the invention inverts the approach by using multiple dividers with deterministic switching. This inversion eliminates the need for post-processing calibration mechanisms.
3Object-generated harmful factors
If calibration circuits are added to reduce phase noise, then noise folding issues are avoided, but overall circuit area and power consumption increase
Solution Approach 1:
The frequency divider is segmented into multiple parallel dividers with different division ratios, which inherently reduces phase noise without requiring additional calibration circuits. This eliminates the power consumption associated with calibration mechanisms while achieving the desired noise reduction.
4Area of stationary object
If a single frequency divider is used with varying divisor, then circuit area is minimized, but quantization error and phase noise increase
Solution Approach 1:
The frequency divider is segmented into multiple parallel dividers with different division ratios. While this increases area compared to a single divider, the patent optimizes the implementation to achieve better frequency division accuracy and reduced quantization error through deterministic switching between dividers, avoiding the need for additional calibration circuits.
Data Source
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AI summary
A fractional-N phase locked loop (PLL) and a sliced charge pump (CP) control method thereof are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a divided clock controller. The first current source provides a first current. The first PFD generates a first detection signal according to a first divided clock, for controlling the first current source, wherein the first divided clock is generated according to an oscillation clock having an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal according to a second divided clock, for controlling the second current source. The divided clock controller controls the second divided clock based on a variable delay relative to the first divided clock, wherein the variable delay is an integer times the oscillation period.