Sliced GPU Architecture Workload Partitioning
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Solution Overview
Problem
As GPUs scale up in physical size, they face issues with clock frequency, design scalability, and workload imbalance, leading to suboptimal performance due to increased voltage not linearly increasing maximum frequency and inefficiencies in memory fetches and pipeline utilization.
Innovation Solution
Implementing a sliced GPU architecture with multiple hardware slices, each comprising a slice primitive controller and various units like geometry pipeline controllers, vertex shaders, and cache units, which partition and distribute graphics workloads efficiently across slices based on processing utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the physical size of the GPU is increased to improve processing performance, then the GPU can handle larger workloads, but the maximum frequency does not increase linearly due to increased wire delay and voltage limitations
Solution Approach 1:
The GPU is divided into multiple independent hardware slices, each capable of processing workloads independently. This segmentation allows each slice to operate at optimal frequency while collectively handling larger workloads, resolving the contradiction between physical size and maximum frequency.
2Speed
If the voltage is increased to raise maximum frequency in larger GPUs, then processing speed may improve, but wire delay prevents linear frequency increase beyond a particular voltage point
Solution Approach 1:
By segmenting the GPU into smaller hardware slices, the physical distance signals must travel within each slice is reduced, thereby decreasing wire delay. This allows each slice to operate at higher frequencies without the wire delay penalties of a monolithic large GPU.
3Productivity
If the GPU is made larger to improve performance, then more processing units are available, but workload distribution becomes unbalanced causing some pipelines to be underutilized
Solution Approach 1:
The system dynamically distributes workloads across hardware slices based on current utilization and workload characteristics. This dynamic allocation ensures balanced resource utilization and prevents pipeline stalls, maintaining high productivity across all slices.
4Productivity
If the GPU size is increased, then more data can be processed in parallel, but memory fetch bottlenecks and internal GPU bottlenecks reduce efficiency
Solution Approach 1:
Segmenting the GPU into independent hardware slices with dedicated memory resources allows parallel memory access without contention. Each slice can independently fetch and process data, eliminating the memory bottlenecks that plague monolithic large GPUs.
Data Source
AI summary
A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.