Sliced NoC Router Architecture for High-Frequency FPGA Data Paths

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

FPGAs face challenges in handling high-throughput data communications due to the lower operating frequencies of user logic, limiting their internal capabilities for high-speed applications such as machine learning and networking.

Innovation Solution

Implementing a sliced router architecture within the FPGA that decomposes the router into multiple slices, each with a subset of external ports, and uses inter-slice communication to achieve full router functionality while reducing wire density and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a traditional router is implemented in FPGA user logic, then routing functionality is achieved, but the operating frequency is limited due to the lower speed of user logic compared to high-frequency interfaces

Engineering Contradiction:
Improveoperating frequencyVSAvoidrouter architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The router is divided into multiple slices, each handling a subset of external ports. Each slice contains input blocks, output blocks, and routing logic that operates independently at high frequency. This segmentation allows the routing function to be distributed across multiple high-speed parallel units rather than implemented as a single complex sequential router in user logic.

Inventive Principle:
Principle #1Segmentation

2Loss of time

If wire density is reduced in the sliced router, then latency is reduced, but the complexity of inter-slice communication increases

Engineering Contradiction:
Improverouting latencyVSAvoidinter-slice communication complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

Inter-slice communication is achieved by transitioning to a different spatial dimension within the FPGA fabric, utilizing the three-dimensional architecture of modern FPGAs. The slices are arranged and connected in a way that exploits vertical and horizontal routing resources, allowing short-latency communication paths that reduce wire density while managing complexity through structured interconnect design.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12506696B2Sliced router for network on a chip
Publication Date: 2025.12.23 ACHRONIX SEMICONDUCTOR CORP
  • US12506696B2 patent drawing
  • US12506696B2 patent drawing
  • US12506696B2 patent drawing

AI summary

A sliced router decomposes a router into a plurality of slices. Each slice has a subset of the input and output ports of the router. One or more of the slices may communicate with a network access point. Adjacent slices communicate with each other. In some example embodiments, there are dedicated physical channels between each slice and each adjacent slice for traffic coming in on or going out on ports of other slices. Within a slice, traffic may be arbitrated onto upstream or downstream channels going to the same output port. Each slice contains one or more crossbars, allowing data received on any input port to be routed to any output port of the slice. The crossbar of each slice is substantially smaller than the crossbar that would be used by a unified router.