Sliced RF Module Timing Synchronization for Low Current
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Solution Overview
Problem
Current RF communication units, particularly those using slicing architectures, face inefficiencies due to high current consumption by noise-sensitive modules like the AND logic gate, which reduces overall efficiency and battery life in wireless devices.
Innovation Solution
A communication unit with a divider module and sliced RF modules, where each module includes a timing synchronization module to synchronize RF signals with a clock signal, reducing unnecessary current draw by selectively enabling only required slices and using a single divide-by-2 module to provide synchronized outputs across multiple slices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If slicing architecture is used to reduce current consumption, then battery life is improved, but noise-sensitive modules require high current to maintain signal integrity
Solution Approach 1:
The RF communication unit is divided into multiple parallel sliced RF modules, each handling a portion of the overall RF signal processing. This segmentation allows the system to achieve high output power through parallel operation while each individual slice can operate at lower current levels, reducing overall power consumption while maintaining signal integrity through distributed processing.
Solution Approach 2:
Multiple sliced RF modules are combined through a combiner port to achieve high output power and signal integrity. The merging of multiple low-current slices produces an aggregate output that meets the required signal strength and noise level specifications without requiring any single module to consume excessive current.
2Productivity
If divide-by-N module drives multiple slices with noise-sensitive circuits, then all slices can operate, but current overhead increases significantly
Solution Approach 1:
The system enables only the necessary number of sliced RF modules based on current communication requirements, rather than operating all slices continuously. This partial action approach reduces current overhead by activating only the minimum required slices, while maintaining the capability to expand to full operation when needed.
Solution Approach 2:
The system dynamically activates and deactivates sliced RF modules based on varying communication demands. This periodic activation pattern allows the divide-by-N module to drive only the currently required slices, reducing average current overhead while maintaining full operational capability when all slices are needed.
3Reliability
If AND logic gate is used to generate LOBUF signal, then signal integrity is maintained, but current consumption increases
Solution Approach 1:
The functionality of the noise-sensitive AND logic gate is replicated across multiple sliced RF modules, each with its own local logic module. This copying approach distributes the signal integrity function across parallel low-current modules, eliminating the need for a single high-current AND gate while maintaining overall signal integrity through the combined output of multiple copies.
Solution Approach 2:
A timing synchronisation module is introduced as an intermediary between the divide-by-N module and the logic modules in each slice. This mediator synchronizes the operation of distributed logic modules across slices, maintaining signal integrity without requiring high current through a centralized AND gate, thereby reducing overall current consumption.
Data Source
AI summary
A communication unit includes at least one divider module arranged to receive a radio frequency (RF) signal and output a divided representation of the RF signal, and a plurality of sliced RF modules. Each of the plurality of sliced RF modules includes: an input for receiving a clock signal; a timing synchronization module arranged to receive the divided representation of the RF signal and synchronize the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; and at least one logic module operably coupled to the timing synchronization module and arranged to receive the clock signal and a synchronized output from the timing synchronization module. A combiner port is arranged to couple a number of synchronized outputs from the plurality of sliced RF modules.