Sliding Block Equalizer for ISI Mitigation
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Solution Overview
Problem
Current Decision Feedback Equalization (DFE) techniques face challenges in high-speed data communications due to increased implementation complexity, power consumption, and area requirements, particularly in submicron CMOS technologies, which limits the scalability and competitiveness of communication receivers.
Innovation Solution
A sliding block signal equalization apparatus and method that partitions a received symbol stream into discrete blocks, allowing independent computation and using a history of symbol decisions to facilitate subsequent decisions, thereby amortizing implementation complexity and reducing power and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional Decision Feedback Equalization (DFE) is implemented to remove ISI from received signals, then detection accuracy is improved, but implementation complexity and power consumption increase significantly
Solution Approach 1:
The patent segments the received symbol stream into discrete blocks and processes each block independently using feed-forward computation rather than recursive feedback. This segmentation eliminates the complex feedback loop while maintaining ISI removal capability, directly resolving the contradiction between detection accuracy and implementation complexity
Solution Approach 2:
The patent uses a history of symbol decisions from previous blocks to facilitate subsequent decisions in current blocks. By performing preliminary symbol estimation and using these results to guide future decisions, the system achieves accurate detection without requiring complex real-time feedback computation
2Productivity
If traditional DFE feedback loop is implemented to operate at high speed, then data throughput is improved, but timing closure becomes increasingly difficult
Solution Approach 1:
By segmenting processing into independent blocks with feed-forward computation, the patent eliminates the recursive feedback loop that causes timing closure difficulties. Each block can be processed independently at high speed without waiting for feedback from subsequent symbols, enabling timing closure at higher data rates
Solution Approach 2:
The patent performs symbol estimation preliminarily using history decisions before final detection. This preliminary action allows high-speed processing because subsequent decisions can be made independently based on pre-computed information rather than requiring sequential feedback computation
3Productivity
If Decision Feed Forward Equalizer (DFFE) is used to achieve timing closure at high frequencies, then data throughput is improved, but power and area overhead increase proportionally with throughput
Solution Approach 1:
The patent segments processing into blocks where only a limited history of symbols needs to be stored and reused. This segmentation limits the power and area overhead to only the necessary history buffer and feed-forward computation, rather than requiring heavy pipelining infrastructure proportional to the full data throughput rate
Data Source
AI summary
A method and apparatus for signal equalization are provided. Multiple decision components are arranged in a sequence, beginning with a history portion and ending with a decode portion. Each decision component performs a decode decision on a symbol. Decode decisions are passed forward to other decision components where they can be used to compensate for intersymbol interference. Decode decision output by the history portion are otherwise discarded, while decode decisions output by the decode portion are output as a decoded signal. In the next decode cycle, input previously provided to the decode portion is again provided to the history portion, in a sliding, overlapping block manner.