Sliding Window Reed-Solomon Decoder for Low-Latency ECC
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Solution Overview
Problem
Traditional serial error correcting code (ECC) decoders struggle with scaling up to high transmission speeds, leading to increased latency and a higher likelihood of silent data corruption, especially with burst errors, as they require multiple clock cycles and grow exponentially in processing complexity with the size of the codeword.
Innovation Solution
Implementing multiple Parallel Error Correctors (PECs) using Reed-Solomon matrix multipliers in hardware, which run concurrently to recompute and compare symbols, allowing for faster error correction and identification of error positions, and using a sliding window list decoder to parallelize the processing of Reed-Solomon encoded codewords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional serial ECC decoders are used, then the processing complexity grows exponentially with codeword size, but transmission speed scaling is limited and latency increases
Solution Approach 1:
The decoder is divided into multiple parallel error corrector units, each handling a portion of the codeword simultaneously. This segmentation allows the system to process larger codewords at higher speeds without exponentially increasing overall complexity, as each unit maintains manageable complexity while working in parallel with others.
Solution Approach 2:
The patent transitions from serial processing (one-dimensional time sequence) to parallel processing (adding spatial dimension with multiple concurrent units). This dimensional change enables the system to achieve high transmission speeds by distributing the computational load across multiple units operating simultaneously, rather than sequentially.
2Reliability
If multiple clock cycles are used for error correction, then correction power increases, but latency increases proportionally
Solution Approach 1:
Multiple error corrector units are prepared and configured in advance to process different portions of the codeword simultaneously. This preliminary arrangement of parallel processing units allows the system to achieve high correction power without the latency penalty of sequential multi-cycle processing, as all corrections occur in parallel within a single or reduced number of clock cycles.
3Device complexity
If serial processing is used for Reed-Solomon decoding, then implementation is simpler, but silent data corruption occurs more frequently with burst errors
Solution Approach 1:
The codeword is segmented into multiple portions, each processed by a dedicated error corrector unit. This segmentation ensures that burst errors affecting one portion do not propagate undetected through the entire decoding process, as other parallel units continue to validate their respective portions independently, thereby reducing silent data corruption.
4Reliability
If correction power is increased to handle larger errors, then error coverage improves, but latency increases with the number of symbols to correct
Solution Approach 1:
The patent adds a spatial dimension to error correction by deploying multiple parallel processing units, each capable of handling correction independently. This allows the system to increase error coverage across the entire codeword without proportionally increasing latency, as all corrections occur concurrently rather than sequentially through a single unit.
Data Source
AI summary
A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.