Slim Integrated Circuit Layout for Display Driver Mounting
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Solution Overview
Problem
The challenge is to reduce the size of display drivers in integrated circuit devices while maintaining their functionality, as shrinking the devices using macrofabrication technology leads to difficulties in mounting and increases costs due to increased glass frame size and pitch differences between circuit blocks.
Innovation Solution
The design includes first to Nth circuit blocks disposed along a specific direction with optimized interface regions, allowing for a slim integrated circuit device configuration that reduces the width in the second direction without causing the layout to become excessively flat, facilitating mounting and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the integrated circuit device is shrunk by using macrofabrication technology, then the chip size is reduced, but it becomes difficult to mount the device and costs increase
Solution Approach 1:
The patent applies asymmetry by arranging circuit blocks in a non-uniform pattern where data driver blocks and other circuit blocks are positioned with different orientations and spacing. This asymmetric layout optimizes the width in the second direction while maintaining mounting feasibility, resolving the contradiction between chip size reduction and ease of manufacture
Solution Approach 2:
The patent transitions from uniform two-dimensional scaling to a dimensionally optimized layout where circuit blocks are arranged with specific width constraints in the second direction. By controlling the width W to satisfy W1+WB+W2≦W1+2×WB+W2, the design achieves size reduction while maintaining manufacturability through dimensional differentiation
2Area of stationary object
If the chip size is reduced by shrinking the integrated circuit device, then cost reduction is achieved, but pitch differences between circuit blocks increase
Solution Approach 1:
The patent applies local quality by assigning different width characteristics to different regions of the chip. Interface regions are designed with specific width constraints while circuit blocks maintain their functional dimensions. This localized optimization reduces overall chip size while maintaining consistent pitch relationships between adjacent circuit blocks, resolving the contradiction between size reduction and manufacturing precision
3Area of stationary object
If the width in the second direction is reduced, then the overall chip area is minimized, but the layout becomes excessively flat
Solution Approach 1:
The patent applies dynamics by creating a flexible layout system where circuit blocks can be positioned at varying distances from interface regions while maintaining the width constraint. This dynamic arrangement allows the layout to adapt to functional requirements without becoming excessively flat, resolving the contradiction between area minimization and shape maintenance
Data Source
AI summary
An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1, a first interface region provided on the D2 side of the circuit blocks CB1 to CBN, and a second interface region provided on the D4 side of the circuit blocks CB1 to CBN. The circuit blocks CB1 to CBN include a data driver block DB and a circuit block other than the data driver block DB. When the widths of the first interface region, the circuit blocks CB1 to CBN, and the second interface region in the direction D2 are respectively W1, WB, and W2, the integrated circuit device has a width W in the direction D2 of “W1+WB+W2≦W<W1+2×WB+W2”.