SLIM Routing Patch Structure for Dense Semiconductor Package Interconnects
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in achieving high routing density and cost-effectiveness, particularly in advanced technology nodes like 10 nm CMOS, where die sizes do not shrink significantly, leading to high defect density and increased costs, and interposers are costly and thick.
Innovation Solution
The use of a silicon-less integrated module (SLIM) with high routing density patches, comprising thin layers of inorganic and organic dielectrics, provides dense trace line densities and reduces costs by allowing die split solutions with finer interconnects, especially in mobile devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor packaging is used with standard routing density, then manufacturing cost is controlled, but routing density is insufficient for advanced technology nodes
Solution Approach 1:
The packaging structure is divided into multiple functional layers including organic substrate, inorganic dielectric layers, and metal trace layers. Each layer is fabricated separately with optimized routing density, allowing high-density interconnects in critical areas while maintaining cost-effectiveness in less demanding regions.
Solution Approach 2:
The patent transitions from planar routing to three-dimensional routing by stacking multiple inorganic dielectric layers with metal traces in between. This vertical dimension enables significantly higher routing density without increasing the horizontal footprint, addressing the needs of advanced technology nodes.
2Productivity
If die size is reduced for advanced technology nodes, then integration density increases, but defect density increases and manufacturing cost increases
Solution Approach 1:
An inorganic dielectric layer acts as an intermediary between the organic substrate and the semiconductor die. This intermediate layer provides mechanical support, thermal management, and electrical isolation, enabling smaller die sizes with reduced defect density by distributing stress and improving manufacturing yield.
3Manufacturing precision
If silicon or glass interposers are used, then routing density is improved, but package cost increases and form factor increases
Solution Approach 1:
The patent employs a composite structure combining organic substrate materials with thin inorganic dielectric layers. This composite approach achieves the high routing density of silicon or glass interposers while maintaining the cost-effectiveness and smaller form factor advantages of organic substrates.
Solution Approach 2:
Thin inorganic dielectric films are deposited on the organic substrate to create high-density routing paths. These thin films provide the necessary electrical isolation and mechanical support without adding significant thickness, enabling compact package form factors with high routing density.
Data Source
AI summary
Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.