3D Memory Stack With Slit Insulation and Pillar Channels
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Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices require complex processes and face challenges in manufacturing, particularly in forming memory layers and vertical channel layers, which can lead to damage and deterioration of memory cell characteristics due to the difficulty in etching memory layers with high aspect ratios.
Innovation Solution
A semiconductor device structure that eliminates the need for pipe transistors by using a stack of conductive and insulating layers with a slit insulating layer, allowing for easier manufacturing and reduced source resistance, where semiconductor pillars act as channel layers and memory layers surround these pillars, avoiding the need for etching memory layers on bottom surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional processes are used to form memory layers and vertical channel layers with high aspect ratios, then three-dimensional memory structure is achieved, but manufacturing complexity increases and memory layer damage occurs
Solution Approach 1:
The source layer is formed in advance before the memory layers are deposited. This preliminary formation of the source layer provides a solid foundation that simplifies subsequent manufacturing steps, allowing vertical channel layers to be formed more easily without requiring complex high aspect ratio etching processes
Solution Approach 2:
Instead of forming high aspect ratio vertical channel layers first and then attempting to etch memory layers on their bottom surfaces, the invention inverts the sequence by forming the source layer first, then depositing memory layers conformally. This reversal eliminates the need for difficult bottom-surface etching operations
2Ease of operation
If memory layers are etched on bottom surfaces of vertical channel layers, then contact to source region is achieved, but memory layer damage and deterioration of memory cell characteristics occur
Solution Approach 1:
The source layer is formed in advance before memory layers are deposited. This preliminary action allows the source contact to be established through the side walls of vertical channel layers rather than requiring etching through the bottom surfaces of memory layers, thus preventing memory layer damage
Solution Approach 2:
The source layer acts as an intermediary structure that enables electrical contact between the source region and external contacts. By forming this intermediary layer first, the patent avoids the need to etch through memory layers, thus protecting them from damage while still achieving the necessary electrical connectivity
3Adaptability or versatility
If pipe transistors are formed to couple source side and drain side memory cells, then memory cell connectivity is achieved, but device complexity and threshold voltage control difficulty increase
Solution Approach 1:
The patent merges the functions of pipe transistors into the word line structure itself. The word lines are configured to extend over both source side and drain side vertical channel layers, effectively combining the coupling function previously requiring separate pipe transistors into the existing word line architecture, thus reducing device complexity
Solution Approach 2:
The word lines serve multiple functions: they provide select signals for memory cell access and simultaneously act as coupling elements between source side and drain side memory cells. This multi-functionality eliminates the need for separate pipe transistors, simplifying the overall device structure while maintaining necessary connectivity
Data Source
AI summary
Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.