Spatial Light Modulator Bit-Plane Control Without ASIC Cost
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Solution Overview
Problem
Existing spatial light modulators (SLMs) are either high-cost due to ASIC control or limited in functionality by FPGA, lacking flexibility and efficiency in low-cost projection applications.
Innovation Solution
A method and system that preprocesses video frames into bit sequences containing data, control signals, and clock information, storing them in non-volatile memory, and uses programmable real-time units (PRUs) to transfer these sequences to volatile memory and GPIO registers in a single clock cycle, enabling direct control of SLM pixel elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ASIC control is used for SLM, then control precision and reliability are improved, but system cost increases significantly
Solution Approach 1:
The patent replaces expensive ASIC with a combination of FPGA and soft-core processor that can be implemented using standard, widely-available components. The system uses off-the-shelf FPGA devices with integrated memory controllers and GPIO interfaces, eliminating the need for custom ASIC design and fabrication while maintaining reliable SLM control through software-based pixel data generation and timing control.
Solution Approach 2:
The patent implements a universal control architecture using FPGA that can control different types of SLMs (DMD, LCoS, LCD) through a standardized interface. The soft-core processor and memory controller work together to handle various video formats and SLM requirements, making the system adaptable to multiple applications without requiring application-specific hardware design.
2Ease of manufacture
If FPGA with limited functionality is used for SLM control, then system cost is reduced, but functionality and flexibility are limited
Solution Approach 1:
The patent implements dynamic control capabilities through a soft-core processor running on FPGA, allowing the system to adapt its behavior based on different operating conditions. The processor can dynamically generate pixel data, adjust timing parameters, and modify control sequences to support various SLM types and video formats, providing flexibility that fixed-functionality FPGA implementations cannot achieve.
Solution Approach 2:
The patent segments the control functionality into distinct modular components: a soft-core processor for high-level control and pixel data generation, a memory controller for efficient data transfer, GPIO interfaces for SLM control signals, and dedicated logic for timing and synchronization. This modular architecture enables independent optimization of each function while maintaining overall system flexibility.
3Speed
If video frames are processed in real-time without pre-processing, then responsiveness is improved, but processing complexity and power consumption increase
Solution Approach 1:
The patent implements pre-processing of video frames into the required pixel data format using a soft-core processor before the data is transferred to the SLM. This preliminary conversion of video formats and generation of control sequences occurs in advance, allowing the main FPGA logic to simply transfer and output the prepared data, thereby reducing real-time processing complexity while maintaining responsive performance.
Data Source
AI summary
An example method includes receiving a video frame including color information for multiple colors; separating the video frame into multiple bit planes for the multiple colors, respectively; generating timing control information for each bit plane of the multiple bit planes; configuring each bit plane with the corresponding timing control information into a bit sequence for that bit plane; and sequentially applying the bit sequences to display the video frame on a spatial light modulator.