Sloped Gate Profile for Higher Contact Area Without Larger Footprint
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase the interfacial contact area between layers without increasing the footprint area, which is crucial for reducing resistance and improving performance in integrated circuits.
Innovation Solution
A method involving a non-horizontally planar profile etching process is used to form a conductive gate with a sloping recessed surface, followed by an etch-retarding layer deposition and controlled etching to create a tunable line end horn profile, enhancing the contact area between the metal gate and overlying layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional planar gate structure is used, then the manufacturing process is simple, but the interfacial contact area between layers is limited
Solution Approach 1:
The patent applies curvature by forming a non-planar, sloped surface on the gate structure instead of a flat surface. The etching process creates a curved profile where the gate interface area is increased through the sloped geometry, allowing greater contact area between the gate and overlying layers without increasing the lateral footprint.
Solution Approach 2:
The patent transitions from a two-dimensional planar interface to a three-dimensional sloped interface. By introducing a vertical component to the gate interface through controlled etching, the effective contact area is increased in the vertical dimension while maintaining the same lateral footprint, effectively adding another dimension to the contact geometry.
2Quantity of substance
If the gate interface area is increased by enlarging the physical dimensions, then the contact area increases, but the footprint area increases
Solution Approach 1:
The sloped, curved profile of the gate structure allows the contact area to be increased vertically without expanding the lateral footprint. The curvature creates additional surface area through the angled interface, enabling more contact area within the same planar dimensions.
Solution Approach 2:
The patent resolves this contradiction by moving the area increase from the lateral plane to the vertical dimension. The sloped gate interface exploits the vertical space above the original planar surface, increasing contact area without requiring additional lateral footprint.
3Productivity
If scaling down semiconductor dimensions is continued, then production efficiency improves and costs decrease, but manufacturing process complexity increases
Solution Approach 1:
The patent changes the geometric parameters of the gate structure by introducing a sloped profile through controlled etching. This parameter change allows the gate to maintain smaller lateral dimensions for scaling while increasing the vertical interface area, thereby improving electrical performance without sacrificing the benefits of continued device scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the effective gate length and reduces channel and contact resistances, thereby improving the performance of semiconductor devices by increasing the contact area while maintaining or reducing the physical dimensions.
Implementation Method 1
perform a non-planar recess process to form a non-planar recessed surface of the gate structure
Implementation Method 2
deposit a first material layer, a second material layer, and a third material layer
Data Source
AI summary
Provided are structures and methods for forming structures with sloping surfaces of a desired profile. A semiconductor structure includes an active region; and a conductive gate overlying the active region, wherein the conductive gate comprises: a plug having a sloped upper surface with a lowest point; and a liner overlying the sloped upper surface, wherein the liner contacts the plug along a gate interface having a gate interface area, wherein a horizontal cross section of the plug at the lowest point of the sloped upper surface has a plug cross-sectional area, and wherein the gate interface area is greater than the plug cross-sectional area.