Sloped Gate Oxide Structure for Leakage-Controlled Multi-Voltage Transistors

The patent applies local quality by creating different gate oxide layer thicknesses in different regions of the semiconductor device. A first gate oxide layer with greater thickness is formed in a first region for high voltage transistors, while a second gate oxide layer with lesser thickness is formed in a second region for low voltage transistors. This allows each region to be optimized for its specific voltage requirement without requiring separate manufacturing processes, thereby reducing overall process complexity while maintaining the ability to form both high and low voltage transistors on the same wafer.

The patent applies curvature by forming a sloping sidewall structure on the gate oxide layer. The sloping sidewall transitions from a vertical or abrupt profile to a gradual incline, which reduces the electric field concentration at the gate oxide-source/drain interface. This curved profile effectively reduces leakage current and improves electrical performance while still using conventional manufacturing techniques to form the gate oxide layer, thus maintaining ease of manufacture.

The patent uses the sloping sidewall curvature to improve manufacturing precision of the source/drain doped region. The gradual incline of the sloping sidewall provides a more controlled interface for source/drain doping, allowing for better definition of the doped region boundaries and improved precision in controlling the doping profile. This curved structure enables more precise manufacturing compared to abrupt edges while still being formable through conventional processes.