Sloped Side RDL for Z-Direction Interconnect
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Solution Overview
Problem
Conventional semiconductor devices face challenges in forming low-cost z-direction electrical interconnects with fine pitch and high I/O density due to the time-consuming and costly nature of forming conductive vias, which are limited by high aspect ratios and prone to voids, and require costly masking and photolithography processes.
Innovation Solution
A semiconductor device with a sloped side surface featuring a conductive layer formed over the surface, including a segment coplanar with the active surface, and an interconnect structure electrically connected to this layer, allowing for z-direction electrical interconnects without the need for conductive vias, thereby reducing manufacturing time and costs while enhancing I/O density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive vias (TSV, THV, TMV) are used for z-direction electrical interconnect, then electrical connectivity is achieved, but the process becomes time-consuming and costly with limited interconnect pitch
Solution Approach 1:
The patent extracts the conductive via formation process entirely from the manufacturing sequence. Instead of forming vias through the die and encapsulant, the invention places the semiconductor die directly onto conductive interconnect structures that extend from the substrate, eliminating the need for TSV, THV, or TMV formation and associated drilling, etching, and filling steps.
Solution Approach 2:
The conductive interconnect structures are formed on the substrate before the semiconductor die is mounted. This preliminary formation of interconnect structures allows the die to be directly connected to conductive pathways without requiring subsequent via formation, thereby improving manufacturing efficiency and reducing process steps.
2Reliability
If conductive vias with high aspect ratio are formed, then z-direction interconnect is achieved, but I/O density is reduced
Solution Approach 1:
The patent transitions from vertical via-based interconnect to a hybrid approach where conductive interconnect structures extend in both vertical and lateral dimensions. The conductive structures emerge from the substrate and can be routed laterally before connecting to the die, allowing for higher I/O density by distributing connections across multiple dimensions rather than being constrained to vertical vias only.
3Reliability
If conventional via formation processes are used, then electrical interconnect is achieved, but voids and defects are formed
Solution Approach 1:
The patent removes the problematic via formation process that creates voids and defects. By eliminating the drilling, etching, and filling operations that form TSV, THV, and TMV, the invention prevents the formation of voids and associated defects while still achieving reliable electrical interconnect through direct contact between die and pre-formed conductive structures.
4Reliability
If Cu-plated conductive pillars are used for interconnect, then z-direction connectivity is achieved, but masking and photolithography add time and cost
Solution Approach 1:
The patent extracts and eliminates the masking and photolithography steps required for Cu-plated conductive pillar formation. The conductive interconnect structures are formed using alternative methods that do not require these complex and time-consuming processes, thereby reducing manufacturing complexity while maintaining z-direction connectivity.
Data Source
AI summary
A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.