Sloped Stacked Capacitor Structure for High Capacitance Density
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Solution Overview
Problem
Conventional capacitors require large areas to achieve high capacitance, leading to increased die area and reduced die output per wafer, limiting the number of dies that can be fabricated from a single wafer.
Innovation Solution
A stacked capacitor design with a capacitor stack featuring multiple dielectric and conductive plates, including a base plate with sloped sides, allowing for increased capacitance without expanding the lateral die area, achieved through a method involving deposition and patterning of photoresist films using a gray-scale mask for etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor design is used, then capacitance is achieved, but die area increases
Solution Approach 1:
The patent transitions from planar capacitor design to three-dimensional stacked capacitor design. Multiple capacitor units are stacked vertically along the z-axis, enabling capacitance scaling in the vertical dimension rather than expanding laterally. This dimensional transition allows achieving higher capacitance values while maintaining a compact die footprint.
Solution Approach 2:
The capacitor structure is divided into multiple discrete capacitor units stacked vertically. Each unit consists of separate dielectric layers and conductive plates, allowing independent formation and connection. This segmentation enables the total capacitance to be the sum of individual unit capacitances, achieving high capacitance through vertical stacking rather than lateral expansion.
2Quantity of substance
If die area is increased to achieve high capacitance, then capacitance increases, but number of dies per wafer decreases
Solution Approach 1:
By stacking capacitor units vertically in the z-dimension, the patent enables high capacitance to be achieved without increasing the lateral die area. This allows more dies to be fabricated from a single wafer while each die still achieves the required capacitance specification through the stacked configuration.
Solution Approach 2:
Multiple capacitor units are nested vertically within a compact die structure. Each capacitor unit is contained within the same lateral footprint, with dielectric layers and conductive plates arranged in alternating stacked layers. This nesting approach maximizes capacitance density within the available die area.
3Area of stationary object
If stacked capacitor structure is implemented, then area consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of multiple capacitor units into a single integrated stacked structure. Multiple dielectric layers and conductive plates are formed simultaneously or in sequence within the same fabrication process flow, rather than creating separate capacitors. This merging approach reduces the number of discrete components and interconnections required.
Solution Approach 2:
The stacked capacitor structure serves multiple functions within a single die: it provides high capacitance value, maintains compact area footprint, and enables vertical integration with other circuit elements. The same stacked architecture can be adapted for different capacitance requirements by adjusting the number of units or dielectric material properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased capacitance while maintaining reduced area consumption, allowing for more efficient use of die space and potentially increasing the number of dies per wafer.
Implementation Method 1
The photoresist film is patterned into a patterned photoresist mask having at least one sloped side with respect to the second surface of the base plate, by introducing light, through a gray-scale mask, to the photoresist film
Implementation Method 2
forming a capacitor stack by deposition
Data Source
AI summary
A stacked capacitor includes a capacitor stack. The capacitor stack includes a base plate having a first surface and a second opposing surface, a first dielectric layer on or over the base plate, and a first conductive plate on or over the first dielectric layer. A second dielectric layer is on or over the first conductive plate. A second conductive plate on or over the second dielectric layer. The capacitor stack has at least one sloped side with at least one slope with respect to the second surface of the base plate.