Slotted Bond Pad Structure to Reduce Dishing in Stacked Wafers
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Solution Overview
Problem
Dishing of bond pads in multi-dimensional integrated chips leads to void formation and poor electrical connections between stacked dies, compromising performance and reliability.
Innovation Solution
Incorporating cavities within the bond pads filled with dielectric material to reduce the overlap with polishing pads during planarization, maintaining a planar top surface and minimizing dishing, thereby improving electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If bond pads are planarized using conventional polishing methods, then a flat surface is achieved, but dishing occurs causing void formation and poor electrical connections
Solution Approach 1:
The bond pad structure is segmented by introducing cavities that divide the continuous bond pad material into separate regions. This segmentation reduces the overlap area with the polishing pad during planarization, thereby minimizing dishing while maintaining overall planarity and electrical connection quality.
2Manufacturing precision
If bond pad overlap with polishing pad is increased to improve planarity, then surface flatness improves, but dishing increases causing void formation
Solution Approach 1:
The bond pad is divided into segmented regions by cavities, which reduces the continuous overlap area with the polishing pad. This segmentation allows the surface to maintain flatness while minimizing the polishing pressure concentration that causes dishing and void formation.
3Ease of manufacture
If conventional bond pad structure is used, then manufacturing is simpler, but dishing leads to void formation and poor electrical connections
Solution Approach 1:
The bond pad fabrication process incorporates cavity formation that segments the bond pad structure. This segmentation can be achieved through standard photolithography and etching processes, maintaining ease of manufacture while significantly improving electrical connection reliability by preventing dishing-induced voids.
4Reliability
If bond pad overlap with polishing pad is reduced to minimize dishing, then void formation decreases, but surface planarity may be compromised
Solution Approach 1:
The cavities create a segmented bond pad structure that reduces polishing pad overlap while the surrounding dielectric material and cavity walls provide support to maintain surface planarity. This dual effect achieves both reduced dishing and preserved flatness.
Solution Approach 2:
The dielectric material filling the cavities acts as an intermediary structure that supports the bond pad segments, maintaining surface planarity while the cavity geometry reduces direct polishing pad contact and minimizes dishing.
Data Source
AI summary
The present disclosure relates integrated chip structure. The integrated chip structure includes one or more interconnects disposed within a dielectric structure over a substrate. A bond pad having a top surface is arranged along a top surface of the dielectric structure. The top surface of the bond pad includes a plurality of discrete top surface segments that are laterally separated from one another by non-zero distances that extend between interior sidewalls of the bond pad, as viewed in a cross-sectional view. The dielectric structure is disposed directly between the interior sidewalls of the bond pad.