Slotted Gate LDMOS Reducing Miller Capacitance
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Solution Overview
Problem
Conventional LDMOS devices suffer from high gate capacitance, leading to significant switching losses in converter circuits, particularly in switching voltage regulators, due to the thin gate oxide overlapping the transition region, which introduces considerable Miller capacitance.
Innovation Solution
The implementation of a slotted gate structure in LDMOS devices, where the gate electrode layer includes openings over the accumulation and isolation regions, maintaining electrical connectivity without external wiring, thereby reducing Miller capacitance and switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional LDMOS device with thin gate oxide overlapping the transition region is used, then the device can achieve proper electrical characteristics, but it introduces considerable Miller capacitance and high gate charge leading to significant switching losses
Solution Approach 1:
The gate electrode layer is segmented by introducing slots (openings) that divide the continuous gate structure into separate regions. These slots are positioned over the accumulation and isolation regions, eliminating gate charges in those areas while maintaining electrical connectivity through the remaining gate portions, thereby reducing Miller capacitance and switching losses
2Reliability
If the gate oxide is made thin to achieve proper device characteristics, then electrical performance is improved, but Miller capacitance increases significantly
Solution Approach 1:
The harmful effect of Miller capacitance is extracted by removing gate oxide material in specific regions through the slot structure. The openings in the gate electrode layer eliminate the gate oxide over the accumulation and isolation regions, directly removing the source of Miller capacitance while preserving the thin gate oxide in the channel region for proper electrical characteristics
3Loss of energy
If a slotted gate structure is implemented to reduce Miller capacitance, then switching losses are reduced, but the gate structure becomes more complex
Solution Approach 1:
The gate structure is modified locally by introducing slots only in specific regions (over the accumulation and isolation regions) rather than uniformly across the entire gate. This localized modification reduces Miller capacitance where it is most harmful while maintaining the simple continuous gate structure in the channel region, achieving energy efficiency without excessive complexity
4Loss of energy
If openings are created in the gate electrode layer over the accumulation and isolation regions, then gate charges are eliminated and Miller capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The slots in the gate electrode layer are formed using preliminary photolithography and etching processes defined by specific design rules (slot width of 0.5-2.0 micrometers, spacing of 0.5-1.0 micrometers). These preliminary structural definitions guide subsequent manufacturing steps, ensuring precise slot positioning over the accumulation and isolation regions while maintaining manufacturability through established process capabilities
Data Source
AI summary
A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.