Single-Crystal Slow-Clock Calibration Using Temperature Feedback
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Solution Overview
Problem
Conventional clock circuits in mobile communication terminals require multiple crystals and oscillating circuits to calibrate slow clocks, leading to increased costs, and modified designs without extra crystals struggle to achieve accurate slow-clock calibration.
Innovation Solution
A method and unit for slow-clock calibration using a single crystal, oscillating circuit, and frequency divider, where the current temperature of the crystal is measured, and a frequency-divide coefficient is calculated and updated based on a data base correlation, allowing for accurate slow-clock signal generation without an extra crystal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single crystal and oscillating circuit are used with a frequency divider, then crystal cost is reduced, but slow-clock calibration accuracy deteriorates
Solution Approach 1:
The patent changes the frequency division ratio parameter dynamically based on detected temperature. The frequency divider adjusts its division ratio according to temperature-compensated calibration data, allowing the single crystal system to achieve accurate slow-clock calibration that compensates for temperature-induced frequency drift, thereby resolving the accuracy deterioration problem
Solution Approach 2:
The patent implements a feedback mechanism where the system detects actual sleep duration and compares it with expected values, then updates calibration data in a database. This feedback loop enables continuous improvement of calibration accuracy for the single crystal system, overcoming the initial precision limitation
2Measurement precision
If two crystals and oscillating circuits are used, then slow-clock calibration accuracy is improved, but device complexity increases
Solution Approach 1:
The patent makes the single crystal and oscillating circuit serve dual purposes: generating both high-frequency clock signals and slow-clock signals through the frequency divider. This multi-functionality eliminates the need for separate crystal and oscillating circuit components, reducing device complexity while maintaining calibration accuracy through temperature compensation
Solution Approach 2:
The patent merges the functions of two separate crystal-oscillator systems into a single integrated system. The frequency divider and temperature compensation mechanism are combined with the single crystal oscillator to perform both high-frequency and slow-clock functions, thereby simplifying the overall device structure
3Quantity of substance
If frequency divider is used to generate both high-frequency and slow-clock signals, then device cost is reduced, but ability to provide both signals simultaneously is lost
Solution Approach 1:
The patent introduces dynamic temperature compensation where the frequency divider's division ratio is adjusted based on real-time temperature detection. This dynamic adaptation allows the single crystal system to accurately generate both high-frequency and slow-clock signals under varying temperature conditions, restoring the signal generation capability that was lost in static single-crystal designs
Data Source
AI summary
A slow-clock calibration method, a slow-clock calibration unit, a clock circuit and a mobile communication terminal are provided. The calibration method includes: obtaining a current temperature of the crystal; searching a unique frequency-divide coefficient corresponding to the current temperature from a preset data base; if the coefficient is found in the data base, inputting the unique coefficient into a frequency divider; if the coefficient is not found in the data base, obtaining an actual sleep length of the mobile communication terminal, if the actual sleep length is not equal to a required sleep length, calculating a required frequency-divide coefficient and updating the data base with the required frequency-divide coefficient, and if the actual sleep length of the mobile communication terminal is equal to the required sleep length, updating the data base with a current frequency-divide coefficient. Accordingly, slow-clock calibration is realized with reduced crystal costs.