Slow-Fast Programming for Distributed Base Station Updates
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Solution Overview
Problem
The distributed architecture of a third-generation CDMA 2000 base station poses challenges for system testing and field updates due to the limited serial channel between local and remote backplanes, resulting in slow test clock frequencies and prolonged programming durations, as well as the difficulty of performing remote field updates without on-site visits.
Innovation Solution
A novel distributed boundary scan test bus architecture that transmits IEEE 1149.1 Boundary Scan TAP signals over a serial channel, utilizing field programmable gate arrays (FPGAs) and optical/digital transceivers for efficient distributed system testing and remote field updates, with a Slow-Fast programming method to adjust clock frequencies based on propagation delay and remote response needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a serial channel is used to connect local and remote backplanes in a distributed base station, then the base station can be deployed flexibly over long distances, but the test clock frequency becomes slow and programming duration is prolonged
Solution Approach 1:
The patent applies dynamics by implementing a dual-mode clocking system that can dynamically switch between slow clock mode (for distributed units requiring propagation delay accommodation) and fast clock mode (for local units). The TCK generator selectively outputs slow or fast clock signals based on the operational phase and target unit, enabling the system to adapt clock speed to operational requirements rather than being constrained to a single fixed speed.
Solution Approach 2:
The patent segments the programming process into distinct phases: initialization phase using slow clock for distributed units, configuration phase using fast clock for local units, and verification phase using slow clock for distributed units. This segmentation allows different clock speeds to be applied to different parts of the programming process, optimizing overall programming efficiency while maintaining compatibility with distributed architecture constraints.
2Ease of operation
If a serial channel is used for communication between distributed units, then remote field updates can be performed, but the update process takes over an hour
Solution Approach 1:
The patent implements dynamic clock frequency adjustment during the update process. The TCK generator switches to fast clock mode during data transmission phases where propagation delay is not critical, and switches to slow clock mode only during phases requiring acknowledgment from distributed units. This dynamic adjustment reduces the overall update duration from over an hour to a more acceptable timeframe while maintaining remote update capability.
Solution Approach 2:
The patent employs periodic action by structuring the update process into repeated cycles of fast data transmission followed by slow acknowledgment verification. This periodic alternation between fast and slow operations allows bulk data to be transmitted quickly while periodically verifying integrity with slow clocked acknowledgments, significantly reducing total update time compared to using slow clock throughout.
3Reliability
If slow clock frequency is used for distributed units, then signal propagation delay is accommodated, but test and programming duration increases significantly
Solution Approach 1:
The patent segments the system into local units and distributed units with different clocking requirements. The TCK generator provides slow clock signals specifically to distributed units over the fiber optic connection where propagation delay is significant, while providing fast clock signals to local units that do not suffer from propagation delays. This segmentation allows each unit type to operate at its optimal clock speed, maintaining signal integrity for distributed units while avoiding unnecessary slow-down for local units.
Solution Approach 2:
The patent introduces an intermediary TCK generator that acts as a mediator between the master control unit and both local and distributed units. This intermediary selectively generates and routes appropriate clock frequencies to different units based on their location and requirements, shielding local units from the slow clock constraint imposed by distributed unit communication requirements.
4Ease of operation
If field programmable gate arrays are used for remote units, then remote field updates are enabled, but programming complexity increases
Solution Approach 1:
The patent implements universality by designing a unified programming interface and control mechanism that works with both local and distributed units regardless of their FPGA configuration. The master control unit and TCK generator provide a single standardized programming interface that automatically adapts to the target unit type and location, hiding the underlying complexity of dual-mode operation from the user and simplifying the field update process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient distributed system testing and significantly reduces remote field update times from over an hour to less than 19 minutes, minimizing downtime and ensuring robust remote maintenance without on-site visits, while maintaining system integrity and reliability.
Implementation Method 1
A single-bit fiber 260 connects the BBU 250 with a radio frequency unit (RFU) 270
Data Source
AI summary
A slow fast programming method for efficient remote field update in distributed base stations overcomes significant fiber propagation delay associated with a remote unit by applying programming data at two clock frequencies. A fast clock frequency is used for programming data phases that do not require a response from the remote unit, and a slow clock frequency is used for programming data phases that require a response from the remote unit. Testing a base unit and a remote unit is also accomplished with more than one clock based on the test dependence on a remote response.