Slow-Wave Coplanar Waveguide With Metal-Filled TSVs
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Solution Overview
Problem
Current on-chip passive components in integrated circuits, such as those used in communications systems, face challenges due to high losses in transmission lines and antennas, necessitating the development of advanced interconnects that promote slow-wave propagation to reduce size and cost.
Innovation Solution
The implementation of a slow-wave coplanar waveguide structure using a substrate with a signal layer and ground plane layer, where metal-filled through-silicon vias are positioned between the signal and ground plane layers, allowing for adjustment of capacitance and characteristic impedance by varying the dimensions and spacing of these vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional transmission lines are used in integrated circuits, then the circuit can be manufactured with standard processes, but the transmission loss is high and the component size is large
Solution Approach 1:
The patent changes the electrical parameters of the transmission line by introducing periodic variations in capacitance through metal-filled through-silicon vias. This creates a slow-wave effect that reduces the phase velocity of signals, thereby reducing transmission loss and enabling compact component designs without requiring complex external structures
Solution Approach 2:
The metal-filled through-silicon vias act as intermediary elements that couple the signal layer and ground plane layer. These vias introduce controlled capacitance variations along the coplanar waveguide, enabling slow-wave propagation while maintaining compatibility with standard CMOS manufacturing processes
2Area of stationary object
If passive components are integrated onto the chip, then the board area is reduced, but the transmission loss increases due to CMOS process limitations
Solution Approach 1:
The patent modifies the transmission line characteristics by introducing periodic capacitance variations through the metal-filled vias. This creates a slow-wave effect that compensates for the inherent losses in CMOS-based integrated circuits, enabling compact passive components with acceptable transmission performance
Solution Approach 2:
The coplanar waveguide structure combines silicon substrate, metal signal and ground layers, and metal-filled through-silicon vias to create a composite transmission line structure. This composite approach enables slow-wave propagation and reduced transmission loss while maintaining integration benefits
3Area of moving object
If the size of passive components is reduced, then the chip area is reduced, but the performance degrades due to increased losses
Solution Approach 1:
The patent uses parameter changes in the transmission line (periodic capacitance variation) to achieve slow-wave effect, which allows compact component design while maintaining signal quality. The reduced phase velocity increases the electrical length within a given physical space, improving signal integrity in compact designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables compact, low-loss, and highly flexible on-chip slow-wave structures that can be fabricated using conventional CMOS technology, reducing the physical dimensions of passive components like delay lines and phase shifters while maintaining desired impedance characteristics.
Implementation Method 1
tuning at least one of a capacitance and characteristic impedance of the coplanar waveguide structure by adjusting a through-silicon via filled with metal
Data Source
AI summary
On-chip, high performance, slow-wave coplanar waveguide with through-silicon via structures, method of manufacture and design structures for integrated circuits are provided herein. The method includes forming at least one ground plane layer in a substrate and forming a signal layer in the substrate, in a same plane layer as the at least one ground. The method further includes forming at least one metal filled through-silicon via between the at least one ground plane layer and the signal layer.