SM3 Compression Circuit Using Carry Skip Adders to Shorten Critical Path
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Solution Overview
Problem
The Cryptographic Hash Algorithm SM3's hardware implementation is resource and time-intensive due to complex iterative compression processes, particularly in the calculation of the compression function.
Innovation Solution
A data compression method utilizing a carry skip adder to perform addition operations in the compression function, specifically for the SM3 algorithm, which includes cascaded 4-bit carry skip adders to accelerate the propagation of carry chains and reduce the critical path length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional adders are used in the SM3 compression function, then the hardware structure is simple, but the calculation efficiency is low and the critical path is long
Solution Approach 1:
The 32-bit adder is segmented into eight 4-bit adders grouped into two sets. Each 4-bit adder processes a specific bit range, and the segmentation allows parallel processing with carry skip logic to bypass sequential carry propagation, thereby reducing the critical path while maintaining functional correctness.
Solution Approach 2:
Carry skip signals are introduced as intermediary control signals between the 4-bit adder groups. These signals act as mediators that can bypass the sequential carry propagation through look-ahead logic, enabling faster computation by predicting and skipping carry chains without requiring full sequential dependency.
2Reliability
If sixty-four iterative compressions are performed, then the SM3 algorithm security is maintained, but the time consumption and resource usage increase significantly
Solution Approach 1:
The message scheduling operations and initial register value preparations are performed in advance before the main iterative compression process. By pre-computing message words and preparing initial states, the actual 64 iterative compressions can proceed more efficiently without redundant setup overhead in each iteration.
Solution Approach 2:
The adder circuit parameters are changed from conventional ripple-carry architecture to carry-skip architecture with specific grouping (eight 4-bit adders). This parameter change in the hardware structure reduces the time complexity of each compression iteration while maintaining the required 64 iterations for security.
3Measurement precision
If the critical path is lengthened for accurate calculation, then the calculation precision is maintained, but the timing performance deteriorates
Solution Approach 1:
The carry skip adder enables the calculation to skip through intermediate carry propagation stages by using look-ahead logic. Instead of waiting for carries to ripple through all 32 bits sequentially, the circuit can skip ahead when carry patterns are predicted, thus reducing the critical path length while maintaining accurate addition results.
Data Source
AI summary
The present application discloses a data compression method and apparatus, an electronic device, and a computer-readable storage medium. The method includes: determining a compression function and each initial register value in present compression; and executing the compression function on the basis of each initial register value, and in the execution process, using a carry skip adder to perform the addition operation in the compression function to obtain the value of each register after the present compression is completed. In the data compression method provided by the present application, the use of the carry skip adder to perform the addition operation in the compression function improves calculation efficiency of the compression function, such that the critical path may be shortened so as to improve overall algorithm performance in the hardware implementation.