SM3 Round-Update Instructions for Faster Hash Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Implementing the SM3 hash algorithm in processors is computationally intensive due to the large number of operations required for each round, particularly XOR, rotate, and other operations, leading to poor performance and significant computational time.
Innovation Solution
Incorporation of SM3 hash algorithm acceleration instructions, specifically the SM3 two round state word update instructions, which update at least four or eight state words in two rounds, reducing the need for separate instructions and optimizing the computational process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SM3 hash algorithm is implemented using conventional processor instructions, then the algorithm can be executed, but the computational intensity and number of operations required make the performance poor
Solution Approach 1:
The patent combines multiple conventional processor instructions into a single custom instruction called SM3RNDS (State Word Round Update). This custom instruction integrates the complex sequence of operations required for one or more rounds of the SM3 hash algorithm, including state word updates, message expansion, and round function executions, into one atomic operation. By merging these operations, the processor can execute hash algorithms significantly faster while reducing the visible complexity from software perspective.
Solution Approach 2:
The custom SM3RNDS instruction is designed to be self-contained, with all necessary operational logic embedded within the instruction itself. When the processor executes this instruction, it automatically performs the complete round update sequence without requiring external intervention or multiple separate instructions. This self-service approach eliminates the need for software to manually orchestrate multiple operations, thereby improving execution speed.
2Productivity
If multiple operations are performed using separate instructions, then each operation can be executed independently, but the total instruction count increases and performance decreases
Solution Approach 1:
The patent merges multiple time-consuming operations into a single instruction execution. The SM3RNDS instruction consolidates state word updates, message expansion calculations, and round function executions that would traditionally require dozens of separate instructions into one atomic operation. This reduction in instruction count directly decreases the time to complete hash computation while maintaining execution throughput.
Solution Approach 2:
The custom instruction is designed with preliminary action built-in, where the processor automatically performs all necessary preparatory operations (such as loading state words, expanding messages, and preparing round inputs) as part of the single instruction execution. This eliminates the time loss that would occur if these operations were performed sequentially through multiple separate instructions.
3Productivity
If the processor executes each operation sequentially, then correctness can be maintained, but the computational intensity reduces efficiency
Solution Approach 1:
The patent combines multiple computationally intensive operations into a single instruction that the processor executes as one unified operation. The SM3RNDS instruction integrates state word updates, message expansion, and round function executions, allowing the processor to maintain high computational efficiency by reducing the total number of operation cycles required while preserving cryptographic correctness through the atomic nature of the instruction.
Data Source
AI summary
A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.