SM4 Acceleration Processor Instruction Set
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Solution Overview
Problem
The SM4 cryptographic algorithm is computationally intensive, leading to poor performance in software implementations due to the large number of operations required for encryption, decryption, and key expansion, which are typically executed in a high instruction count.
Innovation Solution
The introduction of SM4 acceleration instructions and processors that execute these instructions efficiently, reducing the instruction count by performing multiple rounds of encryption, decryption, and key expansion within a single instruction, utilizing optimized round functions and key expansion functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If software implementation of SM4 algorithm is used, then flexibility and ease of operation are maintained, but processing speed and productivity deteriorate due to high instruction count
Solution Approach 1:
The patent introduces dedicated hardware acceleration units as intermediaries between the software layer and the execution layer. These acceleration units include specific circuitry for performing SM4 cryptographic operations, which mediate between the high-level software algorithms and the physical processing resources, enabling fast execution while maintaining software flexibility.
Solution Approach 2:
The patent replaces the conventional software-based mechanical execution of SM4 operations with dedicated hardware circuits. The hardware acceleration units substitute the software instruction execution mechanism with physical circuitry that performs encryption, decryption, and key expansion operations directly through hardware logic, dramatically improving processing speed.
2Productivity
If hardware acceleration units are added, then processing speed improves, but device complexity increases
Solution Approach 1:
The patent segments the SM4 hardware acceleration into distinct functional units: encryption circuits, decryption circuits, and key expansion circuits. Each unit is designed to handle specific operations independently, allowing for modular implementation that reduces overall design complexity while maintaining high processing speed through parallel execution of multiple operations.
Solution Approach 2:
The patent designs the hardware acceleration units to perform multiple functions within a single integrated structure. The acceleration unit can execute encryption, decryption, and key expansion operations using the same basic circuit architecture, reducing device complexity by eliminating the need for separate dedicated circuits for each function while maintaining high processing speed.
Data Source
AI summary
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.