Small-Area EEPROM Array With Shared Capacitor Structure
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Solution Overview
Problem
Conventional non-volatile memory arrays suffer from reduced area efficiency due to the large area occupied by capacitor structures, leading to increased costs and inefficiencies in programming and erasing operations.
Innovation Solution
A small-area EEPROM array design with parallel bit lines, word lines, and common source lines, where memory cells are arranged symmetrically to share common contacts, allowing for simultaneous programming and erasing using specific bias voltage conditions, reducing the overall layout area and fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor structures are used in each memory cell, then non-volatile memory functionality is achieved, but area efficiency is reduced
Solution Approach 1:
The patent merges the capacitor structure from traditional EEPROM cells into a shared structure that serves multiple memory cells simultaneously. Instead of each cell having its own capacitor, a single capacitor structure is shared among multiple cells, dramatically reducing the area occupied by capacitive elements while maintaining the non-volatile memory functionality through shared charge storage.
Solution Approach 2:
The shared capacitor structure performs multiple functions: it serves as the charge storage element for multiple memory cells, acts as a common reference for read operations, and enables bulk programming and erasing operations across the entire array. This multi-functional design eliminates the need for individual capacitors in each cell.
2Ease of operation
If conventional programming and erasing methods are used, then memory cells can be programmed and erased, but large charge pumps are required increasing device complexity
Solution Approach 1:
The patent extracts the high-voltage generation function from traditional charge pumps and replaces it with a simplified voltage boosting mechanism. By using the shared capacitor structure and clever voltage switching, the system generates the necessary high voltages for programming and erasing without requiring complex charge pump circuits, thereby reducing device complexity while maintaining full programming and erasing capability.
Solution Approach 2:
The patent changes the voltage parameters dynamically during operations. By switching between different voltage states (0V, Vcc, and boosted voltages) on the shared capacitor and control lines, the system achieves programming and erasing functions with simpler circuitry. The voltage parameters are changed in a coordinated manner across the array to enable bulk operations.
3Ease of operation
If two bit lines are arranged between neighboring memory cells, then memory cell connectivity is achieved, but area efficiency is reduced
Solution Approach 1:
The patent merges the bit line structure so that a single bit line serves multiple memory cell columns. Instead of having dedicated bit lines for each cell, the bit lines are shared across multiple columns, reducing the number of bit lines required and increasing the spacing between them, which improves area efficiency and reduces routing complexity.
Data Source
AI summary
A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.