Small-Grain Polysilicon Gates for MOSFET Threshold Matching
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Solution Overview
Problem
The challenge of threshold voltage mismatch in metal-oxide semiconductor field-effect transistors (MOSFETs) arises from stochastic variations in gate electrode dopant diffusion due to large polysilicon grain sizes, leading to dopant accumulation at the gate dielectric-to-channel interface and resulting in performance limitations.
Innovation Solution
A chemical vapor deposition process using disilane and hydrogen gas is employed to form a polysilicon layer with a mean grain size of 50 nanometers or less, reducing grain boundary channeling paths and stabilizing threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon grain size is large, then manufacturing is easier, but threshold voltage mismatch increases due to dopant clustering and incomplete activation
Solution Approach 1:
The patent changes the physical-chemical parameters of polysilicon by controlling grain size through deposition conditions (disilane flow rate, pressure, temperature) to achieve a specific grain size range (50-200 nm) that optimizes both manufacturability and threshold voltage matching. This parameter optimization resolves the contradiction by finding the optimal grain size window that balances ease of formation with dopant activation uniformity.
Solution Approach 2:
The patent applies local quality control by creating a specific grain size distribution within the polysilicon layer that is tailored to prevent dopant clustering. The grain size is controlled to be sufficiently small (50-200 nm) to disrupt channeling paths locally, thereby ensuring uniform dopant activation across different locations while maintaining overall layer quality.
2Manufacturing precision
If polysilicon grain size is reduced to 50 nm or less, then threshold voltage matching improves, but manufacturing complexity increases
Solution Approach 1:
The patent manages deposition process complexity by optimizing key parameters: using disilane as the silicon source with controlled flow rates (10-50 sccm), maintaining specific pressure (100-200 mTorr), and controlling temperature (500-700°C). These parameter optimizations enable precise grain size control (≤50 nm) without requiring overly complex process equipment or procedures.
Solution Approach 2:
The patent introduces hydrogen gas as an intermediary in the deposition process. Hydrogen acts as a carrier gas and reaction medium that facilitates controlled disilane decomposition and polysilicon nucleation. This intermediary enables precise grain size control while simplifying the overall deposition chemistry and process management.
3Manufacturing precision
If grain boundary channeling paths are reduced, then dopant diffusion uniformity improves, but deposition time or process duration increases
Solution Approach 1:
The patent achieves rapid formation of fine-grain polysilicon structure by optimizing deposition parameters: using disilane at controlled flow rates (10-50 sccm), maintaining low pressure (100-200 mTorr), and controlling temperature (500-700°C). These parameter settings enable quick nucleation and growth of small grains (≤50 nm) that reduce channeling paths, thereby achieving uniform dopant diffusion without excessive deposition time.
Solution Approach 2:
The patent performs preliminary grain structure formation during the deposition process itself, creating the fine-grain polysilicon structure (≤50 nm) that will subsequently reduce channeling paths. By establishing the optimal grain structure during deposition rather than requiring separate post-processing steps, the method achieves uniform dopant diffusion characteristics while minimizing total process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces threshold voltage variations between nominally identical transistors, enhancing circuit performance and stability by maintaining uniform threshold voltages across MOSFET pairs.
Implementation Method 1
The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate
Data Source
AI summary
An integrated circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) formed in and over a semiconductor substrate. The MOSFET has a gate structure that includes a gate dielectric layer formed the substrate and a gate electrode located over the gate dielectric layer. A pre-metal dielectric layer is over the gate electrode layer, and an electrical contact through the pre-metal dielectric layer connects to the gate electrode. The polysilicon layer has a mean grain size of 50 nanometers (nm) or less.