Interconnect Structure With Smaller Transition Layer Via
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Solution Overview
Problem
The existing interconnect structures in integrated circuits face an increased likelihood of short circuits due to larger via sizes in transition layers, which necessitate the omission of lines to maintain sufficient spacing, leading to a larger chip area and reduced efficiency.
Innovation Solution
Reducing the size of vias in transition layers to allow for the routing of lines with reduced risk of short circuits, thereby enabling a more compact interconnect structure without omitting lines, and optimizing via dimensions to enhance mechanical strength and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the via size in transition layers is increased to mechanically support larger lines, then the mechanical strength is improved, but the distance between the via and the line below decreases, increasing the likelihood of short circuits
Solution Approach 1:
The patent applies different via sizes at different locations: larger vias in non-transition layers for mechanical support, and smaller vias in transition layers to maintain safe distances from lines below. This local differentiation resolves the contradiction by providing mechanical strength only where needed while preventing short circuits in transition zones.
Solution Approach 2:
The patent changes the via size parameter based on the layer type. Transition layer vias have reduced dimensions compared to other layers, allowing the structure to maintain both adequate mechanical support and sufficient clearance from underlying lines to prevent short circuits.
2Reliability
If lines are omitted in the layer below the transition layer to reduce short circuit risk, then the short circuit likelihood is reduced, but the device size increases by about 12%
Solution Approach 1:
Instead of omitting lines globally, the patent applies local quality by using smaller via sizes specifically in transition layers. This allows lines to be maintained in all layers while only the via dimensions are adjusted in critical transition zones, preventing short circuits without requiring line omissions that would increase device size.
3Area of stationary object
If the via size in transition layers is reduced to maintain line density, then the device area is reduced, but the mechanical support capability may be compromised
Solution Approach 1:
The patent applies local quality by restricting smaller via sizes to transition layers where they are needed for spacing, while maintaining larger via sizes in non-transition layers where mechanical support is critical. This ensures mechanical support capability is preserved in appropriate locations while achieving compact dimensions in transition zones.
Solution Approach 2:
The patent applies partial action by reducing via sizes only in transition layers rather than uniformly across all layers. This partial reduction achieves the goal of compact device area while maintaining adequate mechanical support in layers where full via size is retained.
Data Source
AI summary
An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.