Smart Bridge for NAND Flash Memory Core
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND flash memory devices have limited storage capacity and performance due to the occupation of space by periphery circuitry on the same die as the memory core, which restricts the design of flash data storage elements and increases intercell/interwordline interference.
Innovation Solution
Implementing periphery circuitry, such as data latches, state machines, and ECC engines, on a separate smart bridge device using CMOS technology rather than NAND flash technology, allowing for increased storage capacity and ECC capability by relocating these components away from the memory core die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If periphery circuitry is implemented on the same die as the memory core, then device integration is improved, but storage capacity is reduced due to space occupation
Solution Approach 1:
The patent divides the memory device into separate functional components: the memory core die and a peripheral die. The peripheral die houses all periphery circuitry (charge pumps, state machines, row decoders, column decoders, ECC engines) separately from the memory core, allowing each die to be optimized for its specific function while maintaining overall device integration through packaging.
Solution Approach 2:
The patent extracts periphery circuitry from the memory core die and relocates it to a separate peripheral die. This extraction frees up valuable die area on the memory core for additional flash data storage elements, directly increasing storage capacity while maintaining all necessary peripheral functions.
2Device complexity
If periphery circuitry is implemented on the same die as the memory core, then device integration is improved, but intercell interference increases
Solution Approach 1:
By segmenting the device into separate memory core and peripheral circuitry dies, the patent physically isolates sources of electrical interference and noise generation from the sensitive memory storage elements. This spatial separation reduces intercell and interwordline interference while maintaining functional integration through the peripheral die interface.
3Device complexity
If periphery circuitry is implemented on the same die as the memory core, then device integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the device into two separately manufacturable dies with different optimal process requirements. The memory core die can be manufactured using standard NAND flash processes, while the peripheral die can be manufactured using CMOS processes optimized for digital logic and analog circuitry. This segmentation relaxes overall manufacturing precision requirements by allowing each die to be optimized for its specific process.
Solution Approach 2:
The patent changes the manufacturing parameters and process technology used for different parts of the device. The peripheral die uses CMOS technology with different process parameters than the NAND flash memory core, allowing each component to be manufactured under optimal conditions rather than forcing a single process to meet all requirements.
4Device complexity
If ECC engines are implemented on the memory controller, then system architecture is simplified, but ECC capability is reduced in multi-core implementations
Solution Approach 1:
The patent merges the ECC engine functionality into the peripheral die that is directly coupled to each memory core. This integration allows multiple independent ECC engines to operate concurrently with multiple memory cores, providing enhanced error correction capability for each core while maintaining a relatively simple overall system architecture through the unified peripheral die design.
Data Source
AI summary
An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.