Smart Cache Cleaner with Threshold-Based Dirty-Data Copying

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Solution Overview

Problem

Conventional cache systems face challenges such as latency and power inefficiency due to the need to flush 'dirty' data to volatile memory during low power mode transitions, which increases latency and reduces power efficiency.

Innovation Solution

Implementing a cache cleaner controller with a cache cleaner counter, threshold, and interval to manage 'dirty' data, reducing the amount of data to be flushed by tracking and periodically copying data to maintain coherence with volatile memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all dirty data is flushed to volatile memory during low power mode transitions, then data coherence is maintained, but latency increases and power efficiency deteriorates

Engineering Contradiction:
Improvedata coherenceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The cache cleaner controller proactively copies dirty data to volatile memory before low power mode transitions occur, rather than waiting until the transition is triggered. This preliminary action ensures data coherence is already established when the transition happens, eliminating the need for rushed flush operations and reducing latency during actual mode transitions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements periodic cache cleaning operations at predetermined intervals, continuously maintaining data coherence rather than performing single large-scale flushes. This distributes the data copying workload over time, preventing latency spikes during low power mode transitions while maintaining reliability through regular synchronization.

Inventive Principle:
Principle #19Periodic action

2Reliability

If all dirty data is flushed to volatile memory during low power mode transitions, then data coherence is maintained, but power efficiency deteriorates

Engineering Contradiction:
Improvedata coherenceVSAvoidpower efficiency
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

By copying dirty data to volatile memory in advance during normal operation, the system prepares for low power mode transitions without needing to perform energy-intensive flush operations at the moment of transition. This spreads energy consumption evenly over time rather than concentrating it during critical transitions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Periodic cache cleaning distributes energy consumption across multiple small operations rather than one large operation. This improves power efficiency by allowing the system to manage energy usage more predictably and avoid high-power spikes during low power mode transitions.

Inventive Principle:
Principle #19Periodic action

3Loss of time

If cache cleaner controller copies data at predetermined intervals, then data coherence is maintained with reduced latency, but device complexity increases

Engineering Contradiction:
ImprovelatencyVSAvoidcontroller complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The cache cleaner controller monitors its own operation and automatically initiates copying operations based on predetermined intervals and conditions. It self-manages the timing and execution of cache cleaning without requiring complex external control logic, reducing overall system complexity while maintaining low latency through automated periodic action.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12430257B2Smart cache cleaner
Publication Date: 2025.09.30 ADVANCED MICRO DEVICES INC
  • US12430257B2 patent drawing
  • US12430257B2 patent drawing
  • US12430257B2 patent drawing

AI summary

A cache cleaner controller is described. In one or more examples, an apparatus includes a cache directory including status bits associated with cache locations within cache storage and a cache cleaner controller. The cache cleaner controller is configured to detect that a cache cleaner threshold has been reached. The cache cleaner threshold defines that a threshold number of the status bits indicate data maintained at the cache locations, respectively, has been changed. The cache cleaner controller is also configured to cause the data indicated as changed by the status bits to be copied from the cache locations within cache storage to the physical volatile memory.