Smart Card Chip Personalization via FPGA Challenge-Response
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Solution Overview
Problem
Existing methods for personalizing smart card chips are insecure, as they rely on single secrets, software packages that can be leaked, and allow for potential cloning and reverse engineering, especially after the chip is packaged and deployed.
Innovation Solution
A method using a Field Programmable Gate Array (FPGA) device connected to the chip, which initiates a test mode activation through a secret code and random number generation, employing an anti-reverse challenge-response protocol and a disposable hardware module to verify chip presence, ensuring secure personalization by making test mode activation extremely difficult to replicate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If classical personalization methods using dedicated computer stations and software packages are used, then personalization can be performed with simple equipment, but security is compromised due to potential leakage of secrets and software by personnel
Solution Approach 1:
The personalization process is segmented into wafer-level operations where multiple chips are personalized simultaneously before packaging. The system separates the personalization function from the packaging function, allowing security-critical operations to occur at the wafer stage when chips are still grouped together, reducing the need for secure handling of individual personalized cards later.
Solution Approach 2:
A dedicated personalization device with secure hardware architecture acts as an intermediary between the wafer and the final smart card product. This device incorporates secure elements, controlled interfaces, and authenticated communication channels that prevent unauthorized access and data leakage, addressing the security concerns of classical methods.
2Reliability
If personalization is performed after chip packaging, then chips can be individually processed, but security is weakened as physical access and cloning become more feasible
Solution Approach 1:
Personalization is performed as a preliminary action at the wafer level before the chips are packaged into individual smart cards. By personalizing multiple chips simultaneously while they are still mounted on the wafer substrate, the system establishes security credentials before the chips can be physically accessed or removed for cloning attempts.
Solution Approach 2:
The system uses cryptographic copying mechanisms where security credentials are established through authenticated data transfer and cryptographic binding during wafer-level personalization. This creates digital copies of security information that are bound to the chip's unique characteristics, making physical copying or cloning ineffective.
3Reliability
If single secret or software package based authentication is used, then personalization can be implemented with simple protocols, but security is compromised as secrets can be leaked or reverse engineered
Solution Approach 1:
The authentication mechanism uses local quality by implementing different security measures at different stages of the personalization process. The system employs wafer-level authentication protocols, device-specific cryptographic keys, and staged credential distribution that provide tailored security appropriate to each phase, preventing single-point compromise.
Solution Approach 2:
The authentication system uses asymmetry through cryptographic key pairs and asymmetric authentication protocols where the personalization device holds private credentials while the chips verify using public keys. This asymmetric structure ensures that even if public information is exposed, the private secrets remain protected, preventing reverse engineering.
4Reliability
If wafer-level personalization is implemented, then cloning and reprogramming are prevented, but the process becomes more complex and requires specialized equipment
Solution Approach 1:
The system merges multiple functions into the wafer-level personalization process, including authentication, credential distribution, and cryptographic binding, all performed in a single integrated operation while chips are still on the wafer. This consolidation achieves high security without requiring separate complex systems for each function.
Data Source
AI summary
A method and system configured for personalizing at least one chip (IC), intended to be integrated into a smart card, comprising a tester (T) associated to a (Field Programmable Gate Array) FPGA device (WB) connected to the chip (IC), the chip (IC) being part of a wafer (W) comprising an arrangement of a plurality of chips and a disposable hardware module (HM) for verifying presence of the chip (IC) on the wafer (W). The tester (T) sends a first secret code (S1) to the FPGA device (WB), which sends a command (C) to the chip to initiate a test mode activation. The FPGA device (WB) encrypts a second secret code (S2) by using a secret encryption algorithm (E) parameterized with a true random number (R) received from the chip (IC) and the first secret code (S1) to obtain a first cryptogram (M1) which is sent to the chip (IC).The chip (IC) determines a second cryptogram (M2) by carrying out a Boolean function (F) over a result obtained by decryption of the first cryptogram (M1) using the inverse of the secret encryption algorithm (E-) parameterized with the random number (R) and the first secret code (S1). The second cryptogram (M2) is compared with a calculated result F(S2) obtained by carrying out the Boolean function (F) over the second secret code (S2) temporarily stored on the chip (IC). The FPGA device (WB) performs personalization of the chip (IC) only if the test mode of the chip (IC) is enabled by a successful comparison between the second cryptogram (M2) and the calculated result F(S2).