Smart Card Memory Controller Asynchronous Clock Segmentation
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Solution Overview
Problem
Smart cards are vulnerable to power analysis attacks, where attackers can extract secret data by measuring power consumption during cryptographic operations, as the system clock is exposed, facilitating attacks like simple and differential power analysis.
Innovation Solution
A memory controller for smart cards is designed with an internal circuit for cryptographic key processing using a first clock, while a non-volatile memory interface operates with a second asynchronous clock, ensuring the system clock is not exposed, thereby preventing clock-based attacks by using a buffer for data transfer between the two clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock is used for both cryptographic key processing and non-volatile memory interface operations, then the system is simpler to design and implement, but the system becomes vulnerable to power analysis attacks as the clock signal is exposed
Solution Approach 1:
The clock system is segmented into two separate asynchronous clocks: a first clock for cryptographic key processing and a second clock for non-volatile memory interface operations. This segmentation isolates the cryptographic operations from the exposed memory interface clock, preventing attackers from analyzing the clock signal to infer secret key information while maintaining independent optimization of each subsystem.
Solution Approach 2:
A buffer is introduced as an intermediary component between the first clock domain and the second clock domain. This buffer mediates data transfer between the cryptographic processing unit and the non-volatile memory interface, enabling asynchronous communication while preventing direct clock signal exposure and eliminating the need for attackers to correlate clock phases with cryptographic operations.
2Object-affected harmful factors
If separate asynchronous clocks are used for cryptographic key processing and non-volatile memory operations, then power analysis attacks are prevented, but data transfer between the two clock domains becomes more complex
Solution Approach 1:
A buffer serves as an intermediary data structure that receives data from the first clock domain and outputs to the second clock domain. This buffer absorbs the complexity of asynchronous data transfer, providing a simple interface to both clock domains while handling the complex timing coordination internally, thus protecting the cryptographic operations without exposing complex transfer mechanisms.
Solution Approach 2:
Data is prepared and staged in the buffer in advance before being transferred to the non-volatile memory interface. This preliminary action in the buffer allows the cryptographic processing to proceed independently on the first clock while the buffer gradually transfers data to the second clock domain, simplifying the real-time transfer complexity by pre-processing and staging data.
Data Source
AI summary
A memory controller for a smart card including a non-volatile memory can include an internal circuit that is configured to perform cryptographic key processing responsive to a first clock and a non-volatile memory interface circuit for transferring/receiving a signal to/from the internal circuit in synchronization with the first clock and transferring/receiving the signal to/from an external device in synchronization with a second clock that is asynchronous relative to the first clock.