Smart Card Reception Circuit for Rising-Edge Pause Detection

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Solution Overview

Problem

Existing smart card communication systems face deviations in characteristics and communication waveforms due to environmental factors, leading to difficulties in conforming with communication protocols and reduced efficiency in short-range wireless communication.

Innovation Solution

A reception circuit for smart cards that includes a first circuit to restore a wireless signal to a clock signal and a second circuit to generate a synchronization signal based on a comparison with a reference voltage, allowing accurate detection of the rising starting point of a pause in the signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional reception circuits are used for smart card communication, then the basic communication function is maintained, but communication efficiency deteriorates due to deviations in characteristics and waveforms that cause non-compliance with communication protocols

Engineering Contradiction:
Improvecommunication efficiencyVSAvoidprotocol compliance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-charging the capacitor during the pause period before the expected rising edge occurs. This advance preparation allows the voltage to reach the reference voltage at the correct moment, enabling accurate detection of the rising starting point and ensuring protocol compliance without requiring complex real-time processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces conventional analog waveform detection methods with a digital logic-based approach using capacitors, reference voltages, and logic gates. This substitution transforms the detection process into a more precise and reliable electronic comparison system that better handles deviations in communication waveforms

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If the reception circuit uses simple voltage comparison, then the circuit complexity is reduced, but measurement precision deteriorates due to inability to accurately detect rising starting points under waveform deviations

Engineering Contradiction:
Improverising starting point detection accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a capacitor as an intermediary energy storage element between the received signal and the voltage comparison stage. This intermediary component smooths out waveform deviations and provides a stable charging mechanism that enables precise rising starting point detection through simple voltage comparison with a reference voltage

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the detection parameter from direct waveform amplitude comparison to capacitor voltage charging state comparison. By monitoring when the capacitor voltage reaches the reference voltage threshold, the circuit accurately detects rising starting points even under waveform deviations, transforming a complex detection problem into a simple threshold comparison

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12423533B2Reception circuit and smart card including the same
Publication Date: 2025.09.23 SAMSUNG ELECTRONICS CO LTD
  • US12423533B2 patent drawing
  • US12423533B2 patent drawing
  • US12423533B2 patent drawing

AI summary

The present disclosure provides systems and devices including reception circuits for communications between smart cards and card readers. In some embodiments, a reception circuit of a smart card includes a first circuit and a second circuit. The first circuit is configured to receive a wireless signal including a pause, and restore the wireless signal to a clock signal. The second circuit is configured to charge a voltage of a first node based on a first logic level of the clock signal, compare the voltage of the first node with a predefined reference voltage, and output, based on the comparison of the voltage of the first node, a synchronization signal indicating a rising starting time point of the pause of the wireless signal.