Smart Card Random Number Generator Using Clock Cycle Counting
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Solution Overview
Problem
Existing random number generators in electronic components, particularly in smart cards, face challenges in generating secure and variable random numbers due to the invariability of internal clock cycles and instability of external clock cycles, which limits their security and entropy.
Innovation Solution
The solution leverages the difference between internal and external clock cycles to generate random numbers by counting cycles between specific instructions, using the last byte of external clock cycles and combining them with internal clock signals to create a decorrelated clock, and then applying cryptographic functions like DES to enhance randomness, even if internal clock generation is defective.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If internal clock cycles are used to generate random numbers, then the generation process is simple and fast, but the random numbers lack variability and entropy
Solution Approach 1:
The patent combines internal clock cycles with external clock cycles to generate random numbers. The counter counts cycles of an external clock signal during the execution of a fixed number of processor instructions, and the random number is derived from the final counter value. This merging approach maintains the simplicity and speed of internal generation while introducing variability from the external clock's instability and drift, thereby providing both high productivity and reliable security.
2Reliability
If external clock cycles are used to generate random numbers, then variability and entropy increase, but the generation process becomes more complex and slower
Solution Approach 1:
The patent uses a fixed number of processor instructions as a predetermined time interval for counting external clock cycles. This preliminary action establishes a consistent measurement window that ensures the same execution time across different runs, thereby maintaining reproducibility and speed. The randomness arises from the variable number of external clock cycles that occur within this fixed interval due to clock instability, achieving both high reliability and productivity.
3Reliability
If the number of instructions between first and second instructions is increased, then the random number security improves, but the generation time increases
Solution Approach 1:
The patent changes the parameter of instruction count to an optimized value that balances security and speed. By selecting a fixed number of instructions that is sufficiently large to provide adequate entropy from external clock variations but not excessively large to cause unacceptable delays, the system achieves optimal performance. The random number is derived from the last byte of the counter value, maximizing entropy extraction while minimizing generation time.
Data Source
Figure 1~2
AI summary
This smart card (150) conforming to the ISO 7816 standard includes a microcontroller (100) comprising: - a processor (120) clocked by an internal clock signal (SIGINT) in the microcontroller; - a counter (160) capable of counting a number of cycles (NCYC) of a signal from another clock, for example external (SIGEXT) to the microcontroller; - means (120) for generating a random number (VARALEA) from said number.