Smart CAS Burst Continuation for APU Memory Gap Filling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The disparity in data widths between CPU cache lines and GPU graphics objects in unified memory architectures of APUs leads to inefficiencies in memory bandwidth and data bus utilization due to gaps in data transfers, which existing memory standards like LPDDR5 struggle to consistently fill with command interleaving.
Innovation Solution
Implementing a 'smart CAS burst continuation' mechanism in memory controllers that prioritizes and issues memory commands to fill data gaps, optimizing data bus usage by intelligently scheduling memory access requests based on eligibility and timing parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If larger burst length is selected for memory access, then data transfer capacity is improved, but data gaps are created that reduce data bus efficiency
Solution Approach 1:
The memory controller proactively identifies upcoming data gaps in the burst transfer schedule and pre-issues fill commands to other memory banks before the gaps occur. This preliminary action ensures that when data gaps are created by large burst lengths, the data bus is already prepared with additional data to transfer, maintaining continuous utilization without idle cycles.
Solution Approach 2:
The system maintains continuous useful action on the data bus by interleaving burst transfers with gap-filling transfers. When a large burst creates a data gap, the controller immediately issues commands to other banks to fill that gap, ensuring the data bus remains continuously occupied with productive data transfers rather than idle waiting periods.
2Loss of energy
If command interleaving is used to fill data gaps, then data bus efficiency is improved, but other memory requirements such as write-read turnarounds and page prioritizing are compromised
Solution Approach 1:
The memory controller implements a feedback mechanism that continuously monitors the state of memory banks, including open/closed page status, write buffer status, and timing relationships. This feedback information is used to dynamically determine which commands can safely be issued to fill data gaps without violating write-read turnaround requirements or degrading page access performance. The controller adjusts gap-filling commands based on real-time memory state feedback.
Solution Approach 2:
The system dynamically adjusts the gap-filling strategy based on current memory conditions. The controller can adaptively select which banks to use for gap filling, adjust timing of fill commands, and modify the aggressiveness of gap filling based on workload characteristics and memory state, optimizing the balance between data bus efficiency and memory access performance under varying conditions.
Data Source
AI summary
A data processing system includes a data processor and a memory. The data processor is for issuing memory commands including a first memory command that accesses data of a first size. The memory is operative to transfer data of the first size by separating a first portion of data from a second portion of data by a data gap. The data processor is operable to selectively prioritize and issue a second memory command after issuing the first memory command at a time that fills the data gap.