Smart Compute Resistive Memory for Power Reduction
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Solution Overview
Problem
Modern portable electronic devices face power consumption issues due to frequent off-chip memory accesses and CPU operations, leading to reduced battery life and increased thermal dissipation, especially in IoT and AI applications, where conventional memory solutions are inefficient and power-intensive.
Innovation Solution
The integration of a smart compute resistive memory array with an adaptive memory management and control circuitry (AMMC) tightly coupled to an integrated processor, enabling localized processing and adaptive power management to reduce power consumption and latency, allowing computations to be performed within the memory rather than relying on external hosts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If frequent off-chip memory accesses are used, then data storage capacity is improved, but power consumption increases significantly
Solution Approach 1:
The patent merges the memory array with processing circuitry to form an integrated smart memory device. This combination allows data to be stored and processed within the same chip, eliminating the need for frequent off-chip memory accesses while maintaining high data storage capacity. The integrated architecture directly resolves the contradiction by enabling both large storage capacity and low power consumption simultaneously.
Solution Approach 2:
The patent introduces an intermediary processing layer within the memory device itself. This intermediate processing capability allows data to be manipulated and computed directly in the memory array rather than requiring transfers to external CPU, thereby reducing power consumption associated with off-chip accesses while preserving the ability to store large amounts of data.
2Productivity
If CPU operates during ON state to process data, then computing capability is improved, but power consumption increases dramatically
Solution Approach 1:
The patent segments the computing function by implementing a dedicated processing unit within the memory device, separate from the main CPU. This segmented architecture allows data processing to occur in the memory array itself without requiring the main CPU to remain in high-power ON state, thus maintaining computing capability while significantly reducing overall power consumption.
Solution Approach 2:
The memory device performs self-processing by incorporating processing circuitry that can independently handle data computations. This self-service capability allows the memory to process data locally without constantly requiring CPU intervention, thereby maintaining productivity while reducing the power consumption associated with continuous CPU operation.
3Quantity of substance
If off-chip memory accesses are frequent, then data accessibility is improved, but latency increases
Solution Approach 1:
By merging the memory array with processing circuitry on the same chip, the patent creates a tightly integrated system where data can be accessed and processed without leaving the chip. This integration eliminates the latency associated with off-chip memory accesses while maintaining high data accessibility, as all operations occur within the unified memory-device architecture.
Solution Approach 2:
The patent adds a new dimension to the memory hierarchy by implementing processing capabilities within the memory array itself. This dimensional change from purely storage-based architecture to storage-plus-processing architecture enables data to be accessed and processed in-situ, eliminating the time loss associated with traditional off-chip accesses while preserving data accessibility.
4Use of energy by moving object
If adaptive power management is implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The memory device implements self-service power management by incorporating control circuitry that can autonomously adjust power consumption based on operational needs. This self-service capability allows the device to reduce power consumption during low-activity periods without requiring complex external power management systems, thereby reducing overall power consumption while limiting the increase in device complexity to essential internal control functions.
Data Source
AI summary
Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.