Smart Memory Controller Error Correction for Probabilistic RAM
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Solution Overview
Problem
Existing memory systems, particularly those with high error rates and probabilistic tendencies like PCRAM, MRAM, and RRAM, face challenges in reliable operation and data retention due to manufacturing defects and probabilistic behavior, leading to increased error rates and reduced reliability.
Innovation Solution
A smart memory system that incorporates a non-volatile memory controller for dynamic monitoring of failures, error tracking, and automatic correction mechanisms, including re-write operations and error masking, to ensure reliable data storage and retrieval, even in the presence of defective memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If probabilistic-type memory devices (PCRAM, MRAM, RRAM) are used to provide non-volatile storage, then data retention and non-volatility are improved, but error rates increase and reliability deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller continuously monitors write operations and compares expected vs. actual memory states. When errors are detected in probabilistic memory devices, the system automatically initiates corrective actions including re-writing data and adjusting write parameters, thereby maintaining reliability despite the inherently higher error rates of these memory technologies.
Solution Approach 2:
The memory system performs self-correction through automatic error detection and correction mechanisms. The controller autonomously identifies failed writes, retrieves correct data, and re-writes it without external intervention, enabling the system to compensate for the probabilistic nature of these memory devices and maintain operational reliability.
2Reliability
If dynamic error correction and re-write operations are implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a smart memory controller as an intermediary layer between the host system and the probabilistic memory devices. This controller absorbs the complexity of error correction, monitoring, and re-write operations, shielding the host from these complexities while providing reliable data storage. The intermediary handles all error management functions centrally, simplifying the overall system architecture despite the sophisticated error correction mechanisms employed.
3Reliability
If continuous monitoring and automatic correction mechanisms are added, then error rates are reduced, but use of energy increases
Solution Approach 1:
The patent implements periodic monitoring and correction cycles rather than continuous operation. The memory controller monitors write operations at intervals and performs error correction only when necessary, rather than maintaining constant surveillance. This periodic approach significantly reduces power consumption compared to continuous monitoring while still effectively detecting and correcting errors in probabilistic memory devices.
Data Source
AI summary
A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters.