Smart Power Stage Series Addressing With Resistor-Based Mapping
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Solution Overview
Problem
Existing systems face challenges in efficiently addressing multiple power stages in high current applications, particularly in identifying and controlling a large number of semiconductor devices connected in series, leading to complexity and inefficiency in power delivery systems.
Innovation Solution
A series addressing scheme is implemented using resistors to create distinct voltage differences on address pins, combined with offset pins to ensure consistent address mapping across varying numbers of power drivers, allowing for efficient identification and control of multiple power stages through a passive external network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple power stages are connected in series to handle high current applications, then the power delivery capability is improved, but the complexity of addressing and controlling each individual power stage increases
Solution Approach 1:
The addressing function is segmented into multiple bits (ADDR0, ADDR1, ADDR2, ADDR3) that can be independently configured. Each bit corresponds to a specific resistor connection pattern, allowing 64 unique addressing combinations. This segmentation enables systematic identification of each power stage without requiring complex individual addressing circuits for each device.
Solution Approach 2:
Multiple addressing functions are merged into a single shared resistor network. All power stages share the same ADDR pins and resistor array, eliminating the need for separate addressing circuits for each power stage. The merged approach reduces overall system complexity while maintaining the ability to individually address up to 64 power stages through combinatorial resistor connections.
2Ease of operation
If traditional addressing methods are used for multiple power stages, then each power stage can be individually controlled, but the number of required address pins and resistors increases significantly
Solution Approach 1:
The addressing scheme transitions from a linear one-dimensional approach to a multi-dimensional combinatorial system. By using 4 address bits (ADDR0-ADDR3) that can each be independently configured through resistor connections, the system creates a 4-dimensional addressing space that accommodates 64 power stages. This dimensional expansion allows individual control of each power stage while keeping the physical number of pins and resistors manageable.
3Adaptability or versatility
If the number of power drivers varies in the system, then system flexibility is improved, but consistent address mapping across different configurations becomes difficult
Solution Approach 1:
The system uses configurable resistor parameters (presence or absence of resistors R1-R4) to dynamically change the addressing characteristics. By adjusting which resistors are connected in the address network, the system can adapt to different numbers of power drivers while maintaining consistent address mapping. The resistor configurations act as adjustable parameters that define the addressing behavior for any given system configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The scheme enables precise addressing and control of up to 64 power stages with minimal circuitry, reducing complexity and ensuring consistent address mapping regardless of the number of power drivers, facilitating efficient power delivery.
Implementation Method 1
resistors to create distinct voltage differences on address pins
Data Source
AI summary
A semiconductor device package is disclosed that includes an address voltage supply pin connection, an address voltage output pin connection, a first power driver having a first address pin connection and a second power driver having a second address pin connection. The first address pin connection is connected to the address voltage supply pin connection via a resistor. The first power driver is configured to generate a first indication of a first address based on a voltage on the first address pin connection that is obtainable by a controller to determine the first address. The second address pin connection is connected to the first address pin connection and the address voltage output pin connection. The second power driver is configured to generate a second indication of a second address based on a voltage on the second address pin connection that is obtainable by the controller to determine the second address.