Smart Power Stage Rail Bleeding for Fast Shutdown Discharge

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Solution Overview

Problem

Information handling systems face challenges in rapidly draining power rails during shutdowns, leading to potential boot failures due to prolonged energy depletion times, which can exceed several minutes in some cases.

Innovation Solution

A voltage regulator system incorporating a Smart Power Stage (SPS) with high-side and low-side transistors, controlled by a voltage regulator controller, which sets specific states to rapidly bleed both input and output rails to ground, utilizing a combination of control voltages to manage the transistors' operation and enter an idle mode after a predetermined time or when the input rail reaches a certain voltage level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional power down methods are used, then the system can shut down, but the power rails take several minutes to drain, causing boot failures

Engineering Contradiction:
Improveboot failure preventionVSAvoidpower rail depletion time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by activating bleed circuits and control transistors immediately upon detecting a power down event, proactively draining the power rails before the system fully shuts off. This prevents the prolonged depletion period that causes boot failures by initiating the draining process as soon as shutdown is detected, rather than waiting for natural depletion.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the electrical parameters of the power rails by introducing controlled bleed currents through transistors and resistors. By dynamically adjusting the conductivity of control transistors (Q1, Q2) and activating bleed circuits, the system transforms the slow natural depletion process into a rapid controlled draining process, reducing depletion time from minutes to seconds.

Inventive Principle:
Principle #35Parameter changes

2Speed

If the low-side transistor is fully turned on to bleed the output rail, then the output rail drains quickly, but the transistor dissipates significant power

Engineering Contradiction:
Improveoutput rail depletion speedVSAvoidtransistor power dissipation
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent segments the power rail draining process into two distinct phases: first draining the output rail through the low-side transistor, then draining the input rail through the high-side transistor. This segmentation allows each transistor to operate optimally for its specific task, with the low-side transistor fully on for rapid output rail depletion, followed by the high-side transistor handling input rail depletion, thereby managing overall power dissipation efficiently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs periodic action by using pulse-width modulation (PWM) to control the high-side transistor after the initial draining phase. Instead of keeping it fully on continuously, the transistor is pulsed periodically, allowing the input rail to drain in controlled intervals. This reduces continuous power dissipation while still achieving complete depletion, balancing speed and energy consumption.

Inventive Principle:
Principle #19Periodic action

3Speed

If the high-side transistor is kept in linear region or pulsed mode, then the input rail bleeds faster, but the transistor operates in a high-stress condition

Engineering Contradiction:
Improveinput rail depletion speedVSAvoidtransistor operational stress
Core Design Contradiction:
SpeedVSStress or pressure

Solution Approach 1:

The patent applies preliminary action by first fully turning on the low-side transistor to rapidly deplete the output rail before activating the high-side transistor for input rail draining. This preliminary depletion of the output rail reduces the voltage stress on the high-side transistor during subsequent operation, allowing it to operate in linear or pulsed mode with reduced stress while maintaining fast depletion speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuity of useful action by seamlessly transitioning from low-side transistor operation to high-side transistor operation. The bleed state machine ensures that as one transistor completes its draining task, the other is activated without interruption, maintaining continuous power rail depletion. This continuous action allows the high-side transistor to operate in optimized modes (linear or pulsed) without idle periods, reducing overall stress while maintaining speed.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables faster power rail depletion, reducing the risk of boot failures by ensuring all components reach a fully powered-down state within a manageable time frame, typically seconds, compared to previous systems which could take minutes.

Implementation Method 1

The first control voltage may cause the low-side transistor to be fully turned on to bleed an output rail

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

the second control voltage may cause the high-side transistor to be in a linear region or in a pulsed mode to bleed an input rail

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12135596B2Fast bleed of power rails
Publication Date: 2024.11.05 DELL PROD LP
  • US12135596B2 patent drawing
  • US12135596B2 patent drawing
  • US12135596B2 patent drawing

AI summary

A voltage regulator system of an information handling system includes a Smart Power Stage (SPS) and a voltage regulator controller. The SPS includes a high-side transistor and a low-side transistor. The voltage regulator controller detects a normal power down of the information handling system and sets bleed state for the SPS to a first state. Based on the bleed state being set to the first state, the voltage regulator controller provides a first control voltage to the low-side transistor and a second control voltage to the high-side transistor. The first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region. In response to a predetermined amount of time expiring, the voltage regulator controller enters the SPS in an idle mode.