Smart Refresh Semiconductor Devices Using Latch Address Signals
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Solution Overview
Problem
As semiconductor devices become more highly integrated, the reduced distance between memory cells and word lines leads to data loss due to coupling and interference phenomena, necessitating an additional refresh operation to prevent memory cell malfunction.
Innovation Solution
A semiconductor device is configured to perform a smart refresh operation by generating latch address signals from target address signals, and performing adding and subtracting operations on these signals to generate internal address signals, which are used to activate and refresh memory banks, thereby reducing the risk of data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between memory cells and word lines is reduced to increase integration, then device density is improved, but data loss due to coupling and interference phenomena increases
Solution Approach 1:
The patent performs preliminary refresh operations on memory cells before data loss occurs. The system monitors access patterns and proactively refreshes memory cells that are likely to be affected by coupling and interference phenomena, preventing data loss before it happens.
Solution Approach 2:
The patent implements a feedback mechanism that monitors memory cell access patterns and refresh requirements. Based on this feedback, the system dynamically adjusts refresh operations to target specific memory cells that are most susceptible to data loss due to reduced spacing, thereby maintaining data retention while minimizing unnecessary refresh operations.
2Reliability
If additional refresh operations are performed to prevent data loss, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by performing refresh operations only on specific memory cells that are identified as needing refresh based on access patterns and susceptibility to coupling effects. Instead of uniformly refreshing all memory cells, the system targets only the necessary local regions, reducing overall complexity.
Solution Approach 2:
The patent changes the parameter of refresh operation timing and targeting based on monitored access patterns. By dynamically adjusting which memory cells are refreshed and when, the system optimizes data retention while minimizing the complexity of refresh control logic.
3Measurement precision
If smart refresh operation with adding and subtracting operations is implemented, then refresh precision is improved, but circuit complexity increases
Solution Approach 1:
The patent implements self-service by using the existing address signals and simple arithmetic operations (adding and subtracting) to generate precise refresh addresses. The system leverages its own existing signals and basic computational capabilities to achieve precise targeting without requiring complex external address generation circuits.
Solution Approach 2:
The patent replaces complex mechanical or hardware address generation mechanisms with simpler arithmetic operations (adding and subtracting) performed on digital signals. This substitution reduces circuit complexity while maintaining or improving address precision for refresh operations.
Data Source
AI summary
A semiconductor device includes a peripheral circuit and a core circuit. The peripheral circuit enters a smart refresh mode in which a smart refresh operation is performed based on a command. The peripheral circuit generates a latch address signal from a target address signal to output the latch address signal through a global input/output (I/O) line in the smart refresh mode. The core circuit performs an adding operation and a subtracting operation of the latch address signal to generate first and second internal address signals. The core circuit performs the smart refresh operation for first and second banks based on the first and second internal address signals.