Smartcard Clock Recovery Circuit With Fractional Delay Calibration
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Solution Overview
Problem
Existing clock generation circuits in portable devices, such as smartcards, face challenges in achieving low jitter and low power consumption, especially in full-speed USB standards, where high frequency and multiple phases result in significant power consumption.
Innovation Solution
A USB clock circuit with a meter circuit, adder, registers, signal synthesizer, and delay circuit that calibrates the clock signal using received data to minimize jitter and power consumption by optimizing the Step of Time and fractional delay, utilizing a phase generator and comparator to synchronize the clock signal with high precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a very high frequency oscillator with a high number of phases is used to reduce jitter, then jitter is reduced, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic frequency adjustment by switching between a first frequency (higher) and a second frequency (lower) based on communication mode requirements. During calibration and high-precision operations, the higher frequency is used to minimize jitter. During normal data transmission, the lower frequency is used to reduce power consumption. This dynamic adaptation resolves the contradiction by making the oscillator frequency variable rather than fixed at maximum.
Solution Approach 2:
The patent changes the operating frequency parameter of the oscillator based on operational context. The frequency is adjusted from a first value to a second value depending on whether calibration or data transmission is occurring. This parameter change allows the system to optimize jitter performance when needed while minimizing power consumption during routine operations, directly addressing the technical contradiction.
2Ease of manufacture
If IC technology is used for clock generation without correction, then manufacturing is simple, but timing precision is only around 30%
Solution Approach 1:
The patent implements a calibration mechanism that uses feedback from the received data stream to adjust the oscillator frequency. The system counts oscillator cycles during known time intervals (such as USB frame periods) and uses this feedback to calculate and apply frequency corrections. This feedback loop enables the simple IC-based oscillator to achieve high timing precision (better than 1.5% accuracy) without requiring complex correction circuits, thus resolving the contradiction between manufacturing simplicity and precision.
Solution Approach 2:
The calibration system is self-contained within the USB device, using the received data stream itself as the reference for calibration. The device autonomously measures its own oscillator performance and applies corrections without external intervention. This self-service approach maintains manufacturing simplicity while achieving high precision through intelligent self-calibration.
3Object-affected harmful factors
If a longer period of time of the oscillator is used, then parasitic effects are reduced, but frequency accuracy becomes harder to maintain
Solution Approach 1:
The calibration system continuously monitors the oscillator performance and applies real-time corrections to maintain frequency accuracy. By using feedback from the data stream timing, the system compensates for any drift that might occur with longer oscillator periods. This feedback mechanism allows the use of longer periods (which reduce parasitic effects) while maintaining the required frequency accuracy through active correction.
Data Source
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AI summary
One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal f(0) to f(2i-1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal f(0) to j(2i-1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal f(0) to f(2i-1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.