SmartNIC Buffer Management for Cache-Bounded Storage Writes
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Solution Overview
Problem
In storage systems using SmartNICs, continuous Write requests from a host can lead to buffer overflow in the CPU cache, causing low-speed memory access and degraded Write performance due to cache misses, especially when the SmartNIC has lower hardware performance than the controller body.
Innovation Solution
A network interface device converts access requests, allocates buffers for Write data temporarily, and instructs the host to start data transmission before allocating buffers, using reserved memory areas to manage buffer capacity within the cache limits, thereby reducing cache misses and improving Write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If buffers are allocated in the CPU cache of the SmartNIC to avoid low-speed memory access, then Write performance is improved, but the cache capacity is limited and cannot handle continuous Write requests
Solution Approach 1:
The patent divides the buffer storage into two segments: cache memory for high-speed access and ordinary memory for additional capacity. The controller allocates buffers in ordinary memory when cache is full, and uses a buffer management unit to coordinate data transfer between these segments, effectively segmenting the storage hierarchy to resolve the capacity-speed tradeoff.
Solution Approach 2:
The patent introduces a new dimension of buffer management by adding a buffer management unit that operates independently from the CPU cache hierarchy. This unit manages ordinary memory buffers and coordinates with the cache, effectively adding a third layer to the traditional two-layer (cache-DRAM) memory hierarchy.
2Quantity of substance
If the SmartNIC has lower hardware performance than the controller body, then cost is reduced, but Write performance degradation due to cache miss becomes more significant
Solution Approach 1:
The patent introduces a buffer management unit as an intermediary component that mediates between the CPU cache and ordinary memory. This intermediary handles buffer allocation, data transfer coordination, and cache miss management, allowing the SmartNIC to maintain acceptable Write performance despite having lower overall hardware performance than the controller body.
3Loss of time
If buffers are continuously allocated while waiting for Write target data from the host, then data can be immediately stored when arrives, but buffer capacity increases in proportion to the number of Write requests
Solution Approach 1:
The patent applies preliminary action by pre-allocating buffers in ordinary memory before data arrival, but only allocating the minimum necessary capacity based on expected workload. The buffer management unit monitors cache usage and dynamically adjusts ordinary memory buffer allocation, preventing excessive buffer capacity from being reserved while ensuring immediate data storage capability.
Data Source
AI summary
A storage system includes a controller and a network interface device connected to the controller. The network interface device receives an access request from a host, converts the access request into an access request interpretable by the controller, and issues the access request to the controller. In processing in response to a data writing request from the host, the network interface transmits a message for an instruction to start transmission of writing target data to the host, and then allocates a buffer that temporarily stores writing target data, stores the writing target data received from the host in the buffer, and transfers the writing target data stored in the buffer to the controller.