Reconfigurable SmartNIC Packet Pipeline for High-Throughput Flexibility

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Solution Overview

Problem

SmartNICs face a bottleneck due to programmable processors being slow yet flexible, and fixed processors are fast but limited to single tasks, necessitating a solution that balances flexibility and high throughput.

Innovation Solution

A SmartNIC with a plurality of packet processing engines (PPEs) featuring reconfigurable stages and a packet bus that allows parallel processing and dynamic reconfiguration of ALUs per clock cycle, forming a chain where packets are processed by multiple stages with context memories to adjust operations based on packet type.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If programmable processors are used in SmartNICs, then flexibility is improved (can process multiple types of packets), but processing speed deteriorates (programmable processors are slow)

Engineering Contradiction:
ImproveflexibilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent implements dynamically reconfigurable packet processing engines where the architecture can change its configuration based on the type of packet being processed. Each PPE can be reconfigured via context memory to handle different packet processing tasks, allowing the system to adapt its structure in real-time rather than being statically fixed. This dynamic reconfiguration enables the system to optimize for speed by using specialized configurations while maintaining flexibility to handle multiple packet types.

Inventive Principle:
Principle #15Dynamics

2Speed

If fixed-function processors are used in SmartNICs, then processing speed is improved (faster processing), but adaptability deteriorates (can perform only single task)

Engineering Contradiction:
Improveprocessing speedVSAvoidtask versatility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent creates universal packet processing engines that can perform multiple functions through reconfiguration. Each PPE is designed with a base architecture that can be programmed via context memory to handle different packet processing tasks. This multi-functionality is achieved without sacrificing speed because the reconfiguration occurs at the hardware level rather than through software interpretation, allowing the same physical engine to specialize for each task type while maintaining high processing rates.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If reconfigurable PPEs are implemented, then flexibility is improved (can handle different tasks), but device complexity increases (requires context memory and reconfiguration circuitry)

Engineering Contradiction:
Improvetask flexibilityVSAvoidarchitecture complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the packet processing function into distinct modular components: the PPE core logic, the context memory unit, and the reconfiguration interface. Each PPE is divided into multiple stages that can be independently configured. This segmentation allows the complex reconfiguration functionality to be managed in discrete, manageable units rather than as a monolithic complex system, making the overall architecture more tractable while still achieving high flexibility.

Inventive Principle:
Principle #1Segmentation

4Productivity

If multiple PPEs are used in parallel, then throughput is improved (can process more packets), but device complexity increases (requires packet bus and interconnection)

Engineering Contradiction:
ImprovethroughputVSAvoidinterconnection complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple PPEs into a unified parallel processing array that shares common resources such as the packet bus and context memory interface. Rather than giving each PPE completely independent control logic and memory, the design combines these resources at the system level while maintaining functional independence of each engine. This merging approach achieves high throughput through parallel processing while reducing overall complexity by eliminating redundant components across multiple engines.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12585605B2Coarse grained reconfigurable architecture
Publication Date: 2026.03.24 XILINX INC
  • US12585605B2 patent drawing
  • US12585605B2 patent drawing
  • US12585605B2 patent drawing

AI summary

Embodiments herein describe a configurable packet processing architecture for a SmartNIC or other network device. The configurable architecture includes a plurality of PPEs which are communicatively coupled using a packet bus. A packet can be processed in each of the PPEs. For example, each packet may be first processed by PPE 1, then PPE 2, then PPE 3, and so forth. Moreover, the results of processing the packet at a PPE 1 may affect the operation performed on the packet when it reaches PPE 2 or PPE 3. Thus, the PPEs form a chain where the results determined by a first PPE when processing the packet can affect or change the operation a second PPE performs when processing the same packet.