SmartNIC SSD Direct DMA Data Transfer Architecture
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Solution Overview
Problem
Conventional information handling systems face inefficiencies in data storage and retrieval operations due to the use of central memory as a 'bounce' memory and the need for multiple DMA operations, leading to processing cycle occupation and storage delays.
Innovation Solution
The implementation of a Smart Network Interface Controller (SmartNIC) processing system that performs direct memory access (DMA) operations between a SmartNIC buffer memory subsystem and an SSD storage device, eliminating the central memory as a 'bounce' memory and reducing the need for processing cycles, thereby enhancing data storage and retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional data storage operations use central memory as bounce memory and multiple DMA operations, then data can be stored and retrieved, but processing cycles are occupied and storage delays are introduced
Solution Approach 1:
The patent extracts the central memory and central processing system from the data path between networking device and storage device. By creating a direct connection allowing the networking device to perform DMA writes directly to storage devices, the central memory is removed from the critical data storage path, eliminating the bounce memory requirement and associated delays while maintaining data storage completeness
Solution Approach 2:
The patent introduces a buffer memory subsystem as an intermediary component between the networking device and storage device. This buffer memory enables the networking device to complete DMA writes directly to storage without requiring central memory involvement, thus eliminating storage delays while ensuring reliable data transfer through the buffer's temporary holding capability
2Reliability
If conventional data storage operations use central processing system as data storage middleman, then data can be stored, but processing cycles are occupied
Solution Approach 1:
The patent removes the central processing system from the data storage path by enabling direct DMA operations between the networking device and storage device. The buffer memory subsystem facilitates this direct connection, allowing the central processing system to be extracted from the critical data path, thus freeing processing cycles while maintaining reliable data storage through the buffer's coordination capability
Solution Approach 2:
The patent enables the networking device to perform self-service data storage operations by directly writing data to storage devices via DMA through the buffer memory subsystem. This eliminates the need for the central processing system to act as a middleman, freeing processing cycles for other tasks while the buffer memory ensures complete and reliable data transfer
3Productivity
If networking device writes data to central memory system via DMA write operation, then data can be transferred, but central memory is occupied as bounce memory
Solution Approach 1:
The patent extracts central memory from the data transfer path by introducing a buffer memory subsystem that sits between the networking device and storage device. This allows DMA write operations to proceed directly from the networking device through the buffer to storage, maintaining high data transfer speed while eliminating the need to occupy central memory as bounce memory
Solution Approach 2:
The patent segments the memory hierarchy by introducing a dedicated buffer memory subsystem that handles temporary data storage during transfer operations. This segmentation allows the buffer memory to serve as the bounce memory for data transfers between networking device and storage, preserving fast DMA operations while freeing central memory for other purposes
4Productivity
If storage device performs DMA read operation from central memory system, then data can be retrieved, but storage delays occur
Solution Approach 1:
The patent extracts central memory from the data retrieval path by enabling the storage device to perform DMA read operations directly from the buffer memory subsystem. This direct connection eliminates the delay caused by data transfer through central memory, maintaining efficient data retrieval speed while removing the storage delay bottleneck
Solution Approach 2:
The patent implements preliminary action by having the buffer memory subsystem hold data in readiness before the storage device needs it. The buffer memory receives and holds data from the networking device, preparing it for immediate DMA read operations by the storage device, thus eliminating storage delays while maintaining efficient data retrieval
Data Source
AI summary
A networking device/storage device direct write system includes a chassis that houses a Solid State Drive (SSD) storage device coupled to a Smart Network Interface Controller (SmartNIC) networking device. The SmartNIC networking device receives data via a network, stores the data in a SmartNIC buffer memory subsystem that is included in the SmartNIC networking device, and then perform a Direct Memory Access (DMA) operation to transfer the data stored in the SmartNIC buffer memory subsystem to an addressable memory subsystem that is included in the SSD storage device. If the addressable memory subsystem in the SSD storage device is a volatile memory subsystem, the SmartNIC networking device then transmits a persistent storage instruction to the SSD storage device that causes the SSD storage device to transfer the data stored in the addressable memory subsystem to a persistent memory subsystem in the SSD storage device.