SMBus Slave Interrupt Grouping for Multi-Device Alert Handling
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Solution Overview
Problem
Existing system management bus (SMBus) devices struggle with inefficient processing of interrupt requests from multiple slave devices, as each address can only obtain a single slave device address, leading to low system operation performance and difficulty in adjusting operation modes based on the number of connected slave devices.
Innovation Solution
A bus slave device with a setting module, alarm detection module, selection module, interrupt request module, and control module, which sets interrupt request groups and numbers, detects alarm pin levels, selects interrupt modes, and generates master device receiving signals based on pulse width or group addressing to efficiently manage multiple interrupt requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If each alert response address obtains a single slave device address, then the address identification is simple, but the processing efficiency deteriorates when multiple slave devices issue interrupt requests
Solution Approach 1:
The patent segments the interrupt request processing into two parts: the alarm pin status (which can be shared among multiple slave devices) and the slave device address identification (which requires individual processing). By segmenting the interrupt request into group-level alarm detection and individual address identification, the system can efficiently handle multiple slave devices without requiring separate alert response addresses for each device, thus improving processing efficiency while maintaining manageable complexity
Solution Approach 2:
The patent introduces a new dimension of processing by detecting the alarm pin status before address identification. By adding the alarm pin detection dimension to the existing address-based identification dimension, the system creates a two-stage processing approach: first detecting alarm status (shared dimension), then identifying specific slave devices (individual dimension). This dimensional expansion allows efficient handling of multiple slave devices without proportionally increasing complexity
2Adaptability or versatility
If the system architecture is fixed, then the implementation is simple, but the adaptability deteriorates when the number of slave devices changes
Solution Approach 1:
The patent implements dynamics by making the interrupt request processing adaptable to different numbers of slave devices. The system dynamically adjusts its behavior based on which slave devices are connected and their interrupt request states, rather than following a fixed architecture. The master device can flexibly process interrupt requests from any combination of slave devices, allowing the system to adapt to changing configurations without requiring complex rearchitecture
Solution Approach 2:
The patent achieves universality by designing the interrupt request processing to work with any number of slave devices connected to the SMBus. The alarm pin detection mechanism serves multiple slave devices universally, and the address identification process can handle any slave device address format. This multi-functional design allows the same basic architecture to adapt to different slave device configurations without requiring specialized handling for each scenario
Data Source
AI summary
A bus slave device and an interrupt request determination method thereof are provided. The bus slave device sets interrupt request groups and interrupt request numbers to slave devices, respectively. A master device receives an interrupt request through an alarm pin, and each of the slave devices send interrupt request through the alarm pin, and an alarm detection module detects whether the alarm pin is at a low level. A selecting module selects an interrupt mode which is one of a level mode and a pulse mode. An interrupt request module sends or terminates the interrupt request. The master device configures the interrupt request group and the interrupt request number corresponding to the slave devices through the control module to generate a master device receiving signal, and transmits the master device receiving signal to the master device through the data pin and the clock pin.