Redistribution Structure for SMD/IPD Stress Management
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating smaller electronic components into smaller packages without compromising the integrity of the dielectric and metallization layers, leading to potential delamination and cracking issues due to increased stress, which affects the yield and reliability of semiconductor devices.
Innovation Solution
The proposed solution involves a package structure with a redistribution structure that includes a dielectric layer on a metallization layer, featuring under metallization structures with extending portions through openings in the dielectric layer to connect SMD/IPD terminals, reducing stress and mitigating delamination and cracking risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If electronic components are miniaturized and integrated at higher density, then integration density improves, but stress on dielectric and metallization layers increases causing delamination and cracking
Solution Approach 1:
The metallization structure is segmented into multiple layers with different functions: lower metallization for stress distribution and upper metallization for electrical connection. This segmentation allows each layer to optimize for its specific role, reducing overall stress while maintaining high integration density
Solution Approach 2:
The lower metallization layer is designed with specific material properties and geometric characteristics (extended footprint) tailored for stress management in high-density regions, while the upper metallization maintains properties optimized for electrical performance. This local quality differentiation resolves the contradiction between density and stress resistance
2Area of stationary object
If package size is reduced to accommodate smaller components, then area utilization improves, but stress concentration increases leading to delamination and cracking
Solution Approach 1:
The solution extends the metallization structure from a two-dimensional surface pattern into the third dimension by creating extended lower metallization layers beneath the dielectric. This dimensional extension provides additional stress distribution pathways without increasing the package footprint area
Solution Approach 2:
The package employs a composite metallization-dielectric structure where the lower metallization layer acts as a stress-absorbing substrate that complements the upper metallization and dielectric layers. This composite approach enables small package size while maintaining delamination resistance through the synergistic properties of different materials
Data Source
AI summary
Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively. The first opening, the second opening, the third opening, and the fourth opening are physically separated from each other.