SoC Design Framework Using Hierarchical SMDP Reinforcement Learning
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Solution Overview
Problem
The existing SoC design process is fragmented and manual, leading to design errors, high resource consumption, and inefficiencies due to complexity, with no system for generalization and learnability of data generated during chip design.
Innovation Solution
A SoC design framework utilizing artificial intelligence and reinforcement learning techniques to automate the design process, synchronize a hierarchy of Markov Decision Processes (MDPs) and Semi-Markov Decision Processes (SMDPs), and generate optimal chip architectures through a combination of AI agents and neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual implementation of fragmented design flow is used, then flexibility in design process is maintained, but design errors increase and productivity decreases
Solution Approach 1:
The system performs automated functional verification using AI agents that autonomously generate test cases, execute verification, and identify design errors without manual intervention. The verification system serves itself by learning from design data and improving its verification capabilities automatically.
Solution Approach 2:
Manual design processes are replaced with an automated AI-based system that uses machine learning models to perform functional verification, generate test cases, and identify design errors, substituting human mechanical operations with intelligent automated systems.
2Productivity
If automated AI-based design process is implemented, then productivity and design quality improve, but device complexity increases
Solution Approach 1:
The complex AI-based design system is divided into multiple independent AI agents, each responsible for specific verification tasks. These agents operate independently but coordinate through a standardized interface, reducing overall system complexity while maintaining high productivity.
Solution Approach 2:
The AI-based verification system is designed to handle multiple design domains and verification tasks through a universal framework. The same AI infrastructure can perform functional verification, generate test cases, and validate designs across different domains, reducing the need for separate complex systems.
3Loss of time
If functional verification is performed manually, then resource consumption is lower, but time consumption and design errors increase
Solution Approach 1:
The AI system performs preliminary functional verification by generating test cases and executing verification before final design validation. This early verification catches design errors sooner, reducing overall verification time and resource consumption in later stages.
Solution Approach 2:
The verification system uses feedback loops where AI agents analyze verification results, learn from identified errors, and improve subsequent verification processes. This continuous feedback reduces time consumption by focusing verification efforts on critical areas and prevents repeated errors.
Data Source
AI summary
The embodiments herein discloses a system and method for designing SoC by synchronizing a hierarchy of SMDPs. Reinforcement Learning is done either hierarchically in several steps or in a single-step comprising environment, tasks, agents and experiments, to have access to SoC (System on a Chip) related information. The AI agent is configured to learn from the interaction and plan the implementation of a SoC circuit design. Q values generated for each domain and sub domain are stored in a hierarchical SMDP structure in a form of SMDP Q table in a big data database. An optimal chip architecture corresponding to a maximum Q value of a top level in the SMDP Q table is acquired and stored in a database for learning and inference. Desired SoC configuration is optimized and generated based on the optimal chip architecture and the generated chip specific graph library.