SME Instruction Issue With Two-Phase ZA RAW Hazard Tracking
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Solution Overview
Problem
The challenge of efficiently scheduling and issuing Scalable Matrix Extension (SME) instructions in processor devices, particularly in the context of AI and high-performance computing, is exacerbated by the difficulty in detecting and resolving Read-After-Write (RAW) hazards on ZA registers, which are not feasible due to area constraints and the complexity of associating instruction execution results.
Innovation Solution
A two-phase resolution method is employed to address RAW hazards, involving a reduced-precision tracking operation followed by a full-precision tracking operation to select and issue SME instructions without hazards, allowing out-of-order execution where feasible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ZA register renaming is implemented to enable out-of-order execution, then instruction throughput is improved, but area constraints and complexity of associating instruction execution results worsen
Solution Approach 1:
The patent segments the hazard detection process into two distinct phases: a first phase that performs reduced-precision tracking to quickly identify potential hazards, and a second phase that performs full-precision tracking to confirm hazards. This segmentation allows the system to maintain high throughput by quickly filtering out safe instructions while still providing accurate hazard detection when needed, without requiring full renaming complexity for all instructions.
Solution Approach 2:
The patent applies partial action by implementing reduced-precision tracking that examines only critical subsets of ZA register dependencies in the first phase, rather than performing complete tracking on all instructions. This partial tracking approach provides sufficient hazard detection for the majority of cases while significantly reducing the complexity and area requirements compared to full precision tracking for every instruction.
2Device complexity
If in-order scheduling is used to simplify hazard detection, then device complexity is reduced, but instruction throughput deteriorates
Solution Approach 1:
The patent implements a dynamic scheduling approach where the precision of hazard tracking is adjusted based on the instruction being processed. The two-phase tracking system dynamically selects between reduced-precision and full-precision modes, allowing the processor to optimize between throughput and accuracy on a per-instruction basis. This dynamic adaptation enables higher overall throughput compared to static in-order scheduling while keeping complexity manageable.
3Measurement precision
If full-precision tracking is performed on all micro-ops, then hazard detection accuracy is improved, but processing time and complexity worsen
Solution Approach 1:
The patent segments hazard tracking into two phases with different precision levels. The first phase uses reduced-precision tracking that quickly evaluates a subset of dependencies, providing sufficient accuracy for most instructions with minimal time cost. The second phase applies full-precision tracking only when the first phase identifies potential hazards or requires higher accuracy, thereby maintaining overall detection accuracy while significantly reducing average processing time.
Solution Approach 2:
The patent applies partial action by performing full-precision tracking only on a subset of micro-ops that require it, rather than on all micro-ops. The reduced-precision tracking handles the majority of cases efficiently, and full-precision tracking is applied selectively to ensure accuracy when needed. This selective application of full precision maintains hazard detection accuracy while minimizing the time and complexity overhead.
Data Source
AI summary
Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.